| AVS 64th International Symposium & Exhibition | |
| Plasma Science and Technology Division | Wednesday Sessions |
| Session PS-WeM |
| Session: | Advanced BEOL/Interconnect Etching |
| Presenter: | Angélique Raley, TEL Technology Center, America, LLC |
| Authors: | A. Raley, TEL Technology Center, America, LLC J.C. Shearer, IBM Research Division, Albany, NY I.P. Seshadri, IBM Research Division, Albany, NY A. De Silva, IBM Research Division, Albany, NY J.C. Arnold, IBM Research Division, Albany, NY N. Felix, IBM Research Division, Albany, NY H. Cottle, TEL Technology Center, America, LLC A. Metz, TEL Technology Center, America, LLC |
| Correspondent: | Click to Email |
Continued scaling in semiconductor technology nodes has seen the rise of multi patterning for several critical layers, leading to higher costs, variability, and process complexity. EUV direct print patterning can alleviate and address some of these issues. The insertion of this technology was showcased in 20161 by the IBM Alliance for back end of the line (BEOL) metal trenches on their 7nm device. Exploratory efforts have now shifted to enabling the second generation of EUV patterning, targeting sub-36nm pitch resolution with single exposure. In current CAR-based EUV lithography, thin photoresist is used to prevent pattern collapse defectivity in dense line-space regions. This thin photoresist requires careful engineering of the hardmask and underlayer films below to minimize selectivity burden on etch budgets. This paper will first discuss the etch process design differences between current 36nm pitch EUV patterning and what is needed for sub-36nm pitch. Secondly, we will survey several thin hardmask materials and discuss their interactions with various plasma chemistries. For each material, the impact of both gas chemistry and tuning parameter on selectivity and resist roughness will be reviewed. Finally, continuous wave plasma etch performance will be contrasted with a quasi-ALE plasma etch process1,2 as well as other plasma etch schemes designed to widen the patterning process window and enable successful pattern transfer into a typical BEOL metal patterning stack.
This work was performed by the Research Alliance Teams at various IBM Research Facilities
[1] Xie, VLSI, IEDM, p. 2-7, 2016
[2] Cottle et al. AVS 2016 Quasi-ALE Plasma Etching of EUV Photoresist for Contact Profile Control and PR Selectivity Improvement
[3] Vinayak et al. AVS 2014 Plasma Etch Considerations for Roughness Improvements during EUV and DSA Pattern Transfer using Mid Gap CCP