| AVS 64th International Symposium & Exhibition | |
| Plasma Science and Technology Division | Tuesday Sessions |
| Session PS-TuM |
| Session: | Advanced FEOL/Gate Etching |
| Presenter: | Thamarai Devarajan, IBM Semiconductor Technology Research |
| Authors: | Z. Bi, IBM Semiconductor Technology Research T. Devarajan, IBM Semiconductor Technology Research L. Young, IBM Semiconductor Technology Research B. Miao, IBM Semiconductor Technology Research S. Devries, IBM Semiconductor Technology Research N. Loubet, IBM Semiconductor Technology Research C. Yeung, IBM Semiconductor Technology Research J. Zhang, IBM Semiconductor Technology Research A. Greene, IBM Semiconductor Technology Research H. Zhou, IBM Semiconductor Technology Research M. Wang, IBM Semiconductor Technology Research J. Strane, IBM Semiconductor Technology Research Y. Yao, IBM D. Canaperi, IBM Semiconductor Technology Research C. Surisetty, IBM Semiconductor Technology Research |
| Correspondent: | Click to Email |
With transistor scaling in 7nm technology and beyond, fin spike removal and dummy gate silicon pull are considered to be among the most challenging hurdles in FinFET process development. In this paper, we present a plasma free dry chemical etch technique utilizing NF3 and H2 for selective etching of single crystal and polycrystalline silicon at various FinFET device process steps. It was demonstrated that this technique could completely remove poly silicon in vertically high aspect ratio (AR>5) nanosheet FinFET gates with larger process window (overetch budget ~200%), lower gate leakage current and much higher device yield, compared to the technique used in previous generations. Proper surface preparation, queue time control, and etch byproduct removal strategies are discussed. The residue-free etch and etch by-product sublimation mechanisms are also investigated by High Resolution Electron Microscopy (HREM) and Fourier Transform Infrared Spectroscopy (FTIR) surface analysis.