| AVS 64th International Symposium & Exhibition | |
| Plasma Science and Technology Division | Thursday Sessions |
| Session PS+NS+SS+TF-ThM |
| Session: | Atomic Layer Etching I |
| Presenter: | Kazuhiko Endo, AIST, Japan |
| Authors: | W. Mizubayashi, AIST, Japan S. Noda, Tohoku University, Japan Y. Ishikawa, AIST, Japan T. Nishi, AIST, Japan A. Kikuchi, Tohoku University, Japan H. Ota, AIST, Japan P.-H. Su, National Chiao Tung University, Taiwan Y. Li, National Chiao Tung University, Taiwan S. Samukawa, Tohoku University, AIST, Japan K. Endo, AIST, Japan |
| Correspondent: | Click to Email |
Ge is a promising material for use as high mobility channel in future CMOS. For 5-nm-node CMOS and smaller, to attain electrostatic controllability of the gate electrode, a multichannel fin structure is utilized. Fin structure formation in Ge FinFETs on GeOI substrates is mainly performed by ICP etchings. However, ICP etching causes plasma induced damages owing to the ultraviolet (UV) light generated from the ICP and charge up by ionized atoms. A concern is that such etching damage reduces the performance and reliability of Ge-channel CMOS. In this work, to break-through these plasma induced damages, we demonstrated defect-free and highly anisotropic Ge etching for Ge FinFET fabricated by Cl neutral beam etching.
There are two advantages in the neutral beam etching process. 1) The wafer is not exposed by the UV light generated from the plasma through the high-aspect-ratio carbon aperture plate. 2) Ions are efficiently neutralized by collision with the carbon aperture plate. Thus, in neutral beam etching, the influences of the UV light and charge-up can be perfectly eliminated and defect-free etching can be realized.
In the ICP etching, the Ge fin is formed but has a trapezoidal shape. On the other hand, the Ge fin in the case of neutral beam etching can be vertically formed as compared with that in the case of the ICP etching. A channel surface with atomic-level smoothness was confirmed in neutral beam etching while some roughness was observed in the ICP etching. In neutral beam etching without UV light irradiation, the Ge surface is not damaged, and a surface dangling bond is formed only on the atomic layer and it undergoes a chemical reaction with the reactive species [1]. Thus, atomic layer etching can be realized by neutral beam etching.
The |Id|–Vd and |Id|–Vg characteristics of the Ge FinFET fabricated by neutral beam etching are markedly improved as compared with those of the FinFETs fabricated by ICP etching, in n- and p-type FinFETs. gm max for the Ge FinFET fabricated by neutral beam etching is two times higher for the nFinFET and 10% higher for the pFinFET than those of the FinFETs fabricated by ICP etching, regardless of the fin thickness. In the case of neutral beam etching, since there is no etching damage in the Ge fin, the interface state and surface roughness are drastically lowered. This is the reason for the improved gm max for the n- and p-type Ge FinFETs fabricated by neutral beam etching. Thus, the atomic-level flatness and damage-free etching in the Ge fin formation are essential to high performance Ge FinFETs, which can be realized by neutral beam etching.
References
[1] W. Mizubayashi et al., APEX 10, 026501 (2017).