Paper TF2-ThM2
“Patterned-by-Printing” ZnO Vertical TFTs

Thursday, November 10, 2016, 8:20 am, Room 105A

“Patterned-by-printing” uses selective area deposition (SAD) as an alternative approach to printed electronics: an inhibiting polymer ink is printed and the active materials are deposited via spatial atomic layer deposition (SALD). We have previously illustrated the use of this methodology to make planar ZnO thin-film transistors (TFTs) with equivalent device performance to TFTs fabricated from the same materials but patterned by conventional photolithographic means. We have further shown how patterned-by-printing enables freedom in circuit design due to the orthogonal nature of the patterning process, demonstrating facile fabrication of circuits with architectures that can be difficult to obtain using subtractive processing methods.

This talk will address fully patterned-by-printing vertical thin-film transistors (VTFTs), fabricated without any vacuum metallization steps. Using our standard toolset of SALD, inkjet printing and cleaning, we have explored the unique advantages offered by a patterned-by-printing approach for vertical TFT and circuit architectures. In addition to controlling the inhibitor pattern on the substrate by the print pattern, surface structures can be used to control the spatial location of the inhibitor ink via capillary forces. These vertical transistors have liberal design rules and low print resolution requirements as a result of self-aligned source and drain contacts. Starting with a gate structure having a re-entrant profile on the edge, conformal Al₂O₃ gate dielectric and ZnO semiconductor are patterned at low resolution using a printed inhibitor ink and SALD. The same inhibitor ink is printed at the same low resolution so that it is drawn into the reentrant profile, defining the semiconductor channel between SALD-deposited AZO source/drain contacts. The VTFTs have considerably shorter channel lengths than directly obtainable by the printed resolution, and correspondingly higher device performance from a simple additive patterning process. Furthermore, since each step is the same as used for our planar TFTs, circuits having mixed transistor architectures can be used to optimize performance. Individual device characteristics as well as circuit performance will be discussed.