AVS 63rd International Symposium & Exhibition
    Magnetic Interfaces and Nanostructures Tuesday Sessions
       Session MI-TuA

Invited Paper MI-TuA9
Tunneling in III-N Heterostructures for Low Power Electronics

Tuesday, November 8, 2016, 5:00 pm, Room 102B

Session: Magnetic Phenomena in Organic Systems
Presenter: Patrick Fay, University of Notre Dame
Authors: P. Fay, University of Notre Dame
W. Li, University of Notre Dame
L. Cao, University of Notre Dame
K. Pourang, University of Notre Dame
S. Islam, Cornell University
C. Lund, University of California at Santa Barbara
H. Ilatikhameneh, Purdue University
R. Rahman, Purdue University
T. Amin, Purdue University
D. Jena, Cornell University
S. Keller, University of California at Santa Barbara
G. Klimeck, Purdue University
Correspondent: Click to Email

Continuing increases in circuit complexity and capability for logic and computation applications as well as for emerging low-power systems require fundamental advances in device technology and scaling. Due to power constraints, devices capable of achieving switching slopes (SS) steeper than 60 mV/decade are essential if conventional computational architectures are to continue scaling. Similarly, low power systems such as mobile devices and distributed sensing applications also benefit from devices capable of delivering high performance in low-voltage operation. Tunneling field effect transistors (TFETs) are one promising alternative to achieve these objectives. A great deal of work has been devoted to realizing TFETs in Si, Ge, and narrow-gap III-V materials, but the use of III-N heterostructures and the exploitation of polarization engineering in particular offers unique opportunities. From physics-based simulations, GaN/InGaN/GaN heterostructure TFETs offer the potential for achieving switching slopes approaching 20 mV/decade with on-current densities exceeding 100 µA/µm in nanowire configurations. In this talk, the operational principles of III-N-based TFETs will be described, and device design and performance considerations will be discussed. In addition, experimental efforts demonstrating heterostructure backward diodes in III-N heterostructures as well as progress towards nanostructure-based III-N FETs and TFETs will be reviewed.