| AVS 63rd International Symposium & Exhibition | |
| Electronic Materials and Photonics | Tuesday Sessions |
| Session EM+MN-TuM |
| Session: | New Materials and Devices for TFETs, Spintronics, and Extended CMOS |
| Presenter: | Shinichi Takagi, The University of Tokyo, JST-CREST, Japan |
| Authors: | S. Takagi, The University of Tokyo, JST-CREST, Japan M. Takenaka, The University of Tokyo, JST-CREST, Japan |
| Correspondent: | Click to Email |
Since TFETs based on band-to-band tunneling are expected as ultra-low power devices applicable to LSI for IoT , development of the optimum materials, structures and fabrication process have been strongly pursued for realizing both low sub-threshold swing (SS) of sub-60 mV/dec. and high drain Ion/Ioff ratio at the same time. For this purpose, the reduction in the effective band gap is important for enhancing tunneling current. Thus, we are currently focusing planar-type TFETs using Ge/III-V and their hetero-structures.
In this talk, we address two types of planar TFETs utilizing the Ge/strained Si (sSi) hetero-structure and the InGaAs channels. One of the key issues for TFETs is the formation of the steep and high quality source junctions, which provide both high tunneling current and low off current. For InGaAs TFETs, we have introduced solid-phase Zn diffusion through utilizing the inherent diffusion property of Zn in InGaAs creating defect-less extremely-steep profiles. The steepness of the Zn profiles less than 3.5 nm/dec. was obtained, thanks to the diffusion constant of Zn in InGaAs proportional to the square of the Zn concentration, leading to the automatic realization of the steep impurity profile. The small SS of 64 mV/dec and large Ion/Ioff ratio over1E6 have been realized in the planar-type InGaAs TFETs at room temperature.
For tensile strain Si channel TFETs with Ge sources, in-situ doping p+ Ge/sSi source junctions are employed for realizing steep and defect-less tunneling junction formation. Here, the higher Ev edge of the Ge-source and the lower Ec edge of tensile-strained Si result in reduction in the effective band gap, leading to the increase the tunneling probability with maintaining the relatively large Eg of sSi in the drain regions, which can suppress the ambipolar leakage current. The fabricated Ge/sSOI (1.1 %) TFETs show high Ion/Ioff ratio over 1E7 and steep minimum SS of 28 mV/dec.
In conclusion, the enhancement of tunneling probability by utilizing III-V/Ge materials is quite effective in improving the performance of TFETs. Superior source junction formation and MOS interface control technologies are key factors to realize TFETs using III-V/Ge.
This work was partially supported by JST-CREST, and a Grant-in-Aid for Scientific Research (No. 23246058) from MEXT. We would be grateful to Drs. H. Yamada, O. Ichikawa, M. Yokoyama and M. Yamamoto in Sumitomo Chemical Corporation for continuous support on III-V epi substrates, SOITECH for providing strained SOI substrates and, M. Kim, D.-W. Ahn, T. Gotow, T.-E. Bae, M. Noguchi, K. Nishi and S.-H. Yoon in the University of Tokyo.