Invited Paper 2D+NS-FrM7
Pushing the Performance Limit of 2D Semiconductor Transistors

Friday, November 11, 2016, 10:20 am, Room 103B

Two-dimensional semiconductors (2DSCs) such as MoS₂ have attracted intense interest as an alternative electronic material in the post-silicon era. However, the on-current density achieved in 2DSC transistors to date is considerably lower than that of silicon devices. It remains an open question whether 2DSC transistors can offer competitive performance. To achieve a high performance (high on-current) device requires (1) a pristine channel with high carrier mobility, (2) an optimized contact with low contact resistance and (3) a short channel length. The simultaneous optimization of these parameters is of considerable challenge for atomically thin 2DSCs since the typical low contact resistance approaches either degrade the electronic properties of the channel or are incompatible with the fabrication of short channel devices. Here I will first review different strategies that have been developed to optimize these factors, and discuss how we can combine these strategies together to achieve high performance 2DSC semiconductor transistors. In particular, we will discuss a unique approach towards high-performance MoS₂ transistors using a physically assembled nanowire as a lift-off mask for creating ultra-short channel devices with pristine MoS₂ channel and self-aligned low resistance metal/graphene hybrid contact. With the optimized contact in short channel devices, we demonstrate that a sub-100 nm MoS₂ transistor can deliver a record a high on-current density comparing well with that of silicon devices, demonstrating thte exciting potential of 2DSCs for future electronic applications.