Owing to a high critical electric field and high electron mobility, wide band gap materials such as GaN and SiC are being sought for high voltage power electronics applications. In the case of GaN devices, the reliability continues to be a challenge to must be addressed before successful commercialization. In our work, different dielectrics deposited by Atomic Layer Deposition (ALD) have been investigated for improving the threshold voltage stability and dynamic reliability of AlGaN/GaN based MOSHFETs. A novel pulsed-IV-based methodology was developed and demonstrated to be applicable for detecting both shallow and deep traps and implemented on evaluating different high-k and low-k ALD dielectrics. Using physics-based simulation models and experimental data, it was demonstrated that the leakage at the surface of the AlGaN, whether through the passivation dielectric bulk or the dielectric/AlGaN interface, must be minimized to restrict the formation of a “virtual gate” and minimize current collapse. It was also found that an optimal passivation dielectric must create a high density of shallow interface donor traps to quicken the de-trapping of electrons from the “virtual gate” and the recovery of the channel underneath. Combining simulation and experimental results, an optimal set of ALD dielectrics for a reliable gate stack and access-region passivation regions, respectively, was determined and will be discussed. In the area of SiC devices, low inversion channel mobility, caused high density of interface states (Dit) at SiO2/SiC interface, limits the wide adoption of SiC MOS devices. Atomic Layer Deposition offers key advantages in the area of gate dielectrics such as good film quality, low substrate damage, superior uniformity, precise thickness control, and low process temperature. Additionally, deposited SiO2 enables interface engineering to independently control the interface properties. To enhance the channel mobility and maintain good overall gate dielectric properties, a thin layer of a different dielectric material can be inserted to improve interface properties and high quality deposited SiO2 can be used as the bulk gate dielectric. We have demonstrated a novel interface engineering technique utilizing ultra thin lanthanum silicate (LaSiOx) at the SiC/dielectric interface and ALD SiO2 as the bulk gate dielectric. The lanthanum silicate interface engineering dramatically improves the mobility of 4H-SiC metal oxide semiconductor field effect transistors (MOSFETs) and is attributed to the large driving force of La2O3 to react with SiO2.