Paper NS-TuP18
A New Alternative for Silicon Thinning using NH₄OH Solution Wet Etching for 3D MOS Transistors

Tuesday, October 20, 2015, 6:30 pm, Room Hall 3

Tetramethylammonium hydroxide (TMAH) aqueous solutions, which are the silicon orientation-dependent wet etching, have been used for silicon thinning to get silicon nano (SiNWs) or sub-micron (SiSMWs) wires. These wires can be used as the conduction channel for three-dimensional (3D) Metal-Oxide-Silicon (MOS) transistors, such as FinFETs and JunctionLess, respectively. In this work, instead of TMAH, ammonium hydroxide (NH₄OH) solutions (concentration of 9% wt) are used to get SiNWs and SiSMWs, because also these solutions are silicon orientation-dependent wet etching. Furthermore, NH₄OH solutions are cheaper and fully compatible with CMOS technology. Silicon wafers with (100) crystallographic orientation were used. On these wafers, after RCA cleaning, 330 nm thick SiO₂ layer was grown using thermal oxidation. Lithography, SiO₂ etching (using HF solution) and organic cleaning (to remove photoresist) steps were carried out to define lines of SiO₂ (masking oxide) with width of 3 µm and spacing of 7 µm between lines. Reactive Ion Etching with SF₆ plasma was carried out, resulting in silicon three-dimensional (3D) mesa structures under SiO₂ lines. The 3D mesa sidewalls are the <110> planes and the Si surface between the mesa structures are the <100> plane. After anisotropic etching using NH₄OH solution, Optical (OM) and Scanning Electron (SEM) Microscopy analysis were used to get images of top and side views of samples. The results presented that the <111> planes of Si surface with (100) crystallographic orientation between the mesa structures (spacing of 7 µm) were exposed, resulting a V-groove shape, while, the lateral etching under SiO₂ of <110> plane mesa sidewalls occurred, with consequent thinning of these 3D structures. Using the etching process time and 3D structure measurements extracted from OM and SEM , the lateral etch rate under SiO₂ of <110> plane mesa sidewalls of 110 nm/min was obtained. It is important to notice that the sidewalls are smooth, which is a mandatory requirement to fabricate SiNWs and SiSMWs for 3D conduction channel for FinFETs and JunctionLess transistors. Thus, using our method to get silicon thinning with NH₄OH solution, both devices have been fabricated on Si and SOI wafers, with (100) crystallographic orientation surfaces, respectively. On both wafers, the lateral etch rate under SiO₂ of <110> plane 3D mesa sidewalls of 110 nm/min was repeated and SiNWs and SiSMWs were obtained, indicating that our NH₄OH solution is a new alternative to get 3D nanostructures on Si substrates. The electrical characteristics of these devices are going to present in the conference.