| AVS 62nd International Symposium & Exhibition | |
| Electronic Materials and Processing | Tuesday Sessions |
| Session EM-TuP |
| Session: | Electronic Materials and Processing Poster Session |
| Presenter: | Cássio Almeida, UNICAMP, Brazil |
| Authors: | C.R. Almeida, UNICAMP, Brazil L.P.B. Lima, UNICAMP, Brazil H.T. Obata, University of Campinas, Brazil M. Cotta, University of Campinas, Brazil J.A. Diniz, UNICAMP, Brazil |
| Correspondent: | Click to Email |
N+-InGaP and N+-GaAs layers were grown by Chemical Beam Epitaxy (CBE) on GaAs substrates with (001) orientation. Two group of samples with N+-InGaP (350 nm)/GaAs-buffer layer (300 nm)/GaAs S.I. (Semi-Insulating) and N+-GaAs (300 nm)/GaAs-buffer layer (300 nm)/GaAs S.I. were obtained. X-Ray diffraction (XRD) analysis was used in order to determine the InGaP lattice mismatch on GaAs. N+-InGaP lattice-matched layers on GaAs were obtained using a growing temperature of 550oC during the process in CBE reactor, while, for N+-GaAs on GaAs samples, the temperature was 550oC. By Hall measurements, a silicon doping of 10+18 cm-3 was extracted for both group of samples, indicating the formation of N+-type layers. These samples are being used for MOS Junctionless (JL) Transistors applications, because III-V semiconductors present higher electron mobility values than silicon. These JL transistors (with three terminals: gate, source and drain) are being fabricated using Focused Ion Beam (FIB) System, based on similar process steps of the JL devices, which were fabricated on Silicon-on-Insulator (SOI) substrate[1]. Thus, Gallium (Ga+) Focused Ion Beam (FIB) is used to define the III-V (InGaP or GaAs) nanowires (III-VNW), which are the electron conduction channel between source and drain, and for depositions of SiO2 (as gate dielectric) and Pt (as gate, drain and source electrodes) layers[2]. Finally, drain-source current (IDS) versus drain-source voltage (VDS) and drain-source current (IDS) versus gate-source voltage (VGS) measurements of Junctionless devices will be extracted and will be able to indicate if these InGaP or GaAs nanowires are suitable for Junctionless transistors applications.
References:
[1] Lima, L. P. B., et al. "Junctionless Fabrication on SOI Wafers Using Focused Ion Beam Milling and Al Diffusion."ECS Transactions 49.1 (2012): 367-374.
[2] dos Santos, Marcos V. Puydinger, et al. "Fabrication of p-type silicon nanowires for 3D FETs using focused ion beam."Journal of Vacuum Science & Technology B 31.6 (2013): 06FA01.