AVS 62nd International Symposium & Exhibition
    Electronic Materials and Processing Tuesday Sessions
       Session EM-TuM

Invited Paper EM-TuM1
Secret Ingredients in Thin-TFET: A 2D Material-based Transistor

Tuesday, October 20, 2015, 8:00 am, Room 210E

Session: Beyond CMOS: Materials and Devices for a Post CMOS Era
Presenter: Grace Huili Xing, Cornell University
Correspondent: Click to Email
Thin-TFET stands for Two-dimensional Heterojunction INterlayer Tunnel Field Effect Transistor [1]. This name was coined by my student, Mingda Oscar Li, based on one of the device concepts we submitted in the LEAST center proposal. The rationale behind this device concept was derived from our earlier work on III-V based TFETs, in particular, TFETs with tunneling aligned with the gate field [2] and our investigations on the impact of band alignment (straddling [3], staggered and broken-gap [4]) on TFET. In the recent benchmarking exercise [5,6], a few more intriguing features were discovered in this 2D embodiment of the TFET with tunneling aligned with the gate field, in additional to being the ultimate scaled TFET down to the atomic thickness. [1] M. Li et al, JAP, 074508 (2014). [2] Y. Lu et al. EDL, 655 (2012). [3] G. Zhou et al. EDL, 782 (2012); G. Zhou et al. EDL, 1516 (2011). [4] G. Zhou et al. DRC (2011); G. Zhou et al. IEDM (2012). [5] M. Li et al. J-EDS, 200 (2015); [6] D. Nikonov et al., J. Exploratory Solid-State Computational Devices and Circuits, 10.1109/JXCDC.2015.2418033 (2015).