AVS 62nd International Symposium & Exhibition
    Electronic Materials and Processing Monday Sessions
       Session EM+NS+PS-MoM

Paper EM+NS+PS-MoM3
Border Trap Analysis and Reduction for ALD High-k InGaAs Gate Stacks

Monday, October 19, 2015, 9:00 am, Room 210E

Session: More Moore! Materials and Processes to Extend CMOS Another Decade
Presenter: Kechao Tang, Stanford Univ.
Authors: K. Tang, Stanford Univ.
R. Winter, Technion – Israel Inst. of Tech.
T. Kent, UC, San Diego
M. Negara, Stanford Unive.
R. Droopad, Texas State Univ.
A.C. Kummel, UC, San Diego
M. Eizenberg, Technion – Israel Inst. of Tech.
P. McIntyre, Stanford Univ.
Correspondent: Click to Email

For future high performance III-V n-channel MOS devices, In0.53Ga0.47As is a promising material for the channel due to its high electron mobility. Atomic layer deposited (ALD) Al2O3 has a large conduction band offset to InGaAs and can form a low defect-density interface with InGaAs [1]. ALD-HfO2 can achieve a very low EOT (effective oxide thickness) with low gate leakage [2]. Therefore, both of these oxides have received extensive attention as candidate dielectric layers for InGaAs nMOSFETs. Apart from the well-known oxide/InGaAs interface charge traps that may pin the Fermi level of the channel, traps in the oxide layer, called border traps, may also reduce the charge in the channel and thus degrade the on-state performance of InGaAs MOSFET devices. We report a study of the effects of various approaches to reduce the density of border traps (Nbt), such as variation of the ALD temperature, and of post-gate metal forming gas (5% H2/95% N2) anneal (FGA) conditions.

Experimental methods employed include quantitative interface trap and oxide trap modeling [3, 4] of MOS capacitor data obtained over a range of frequencies and temperatures. We find that MOS capacitors fabricated using trimethylaluminum (TMA)/H2O at an ALD temperature of 120°C have a considerably lower border trap density while maintaining a low interface trap density (Dit) compared to samples prepared with a more standard 270°C Al2O3 ALD temperature. It is also found that large-dose (~6,000 L) exposure of the In0.53Ga0.47As (100) surface to TMA immediately after thermal desorption of a protective As2 capping layer in the ALD chamber is an important step to guarantee the repeatability of high quality Al2O3/InGaAs samples made at Al2O3 ALD temperatures much lower than 270°C. The reduction of Nbt is consistent with time-of-flight secondary ion mass spectrometry depth profiles that show more effective hydrogen incorporation in the low-temperature ALD-grown Al2O3 films during post-gate FGA.

The Nbt of Al2O3 under various conditions will be compared with that of low-temperature ALD-grown HfO2 films on InGaAs substrates. For the HfO2 case, we also confirm the independence of border trap response on the electrical measurement temperature and check the influence of the crystal orientation of the InGaAs surface on MOS interface characteristics.

This work was supported by the US-Israel Binational Science Foundation.

References

[1] J. Ahn et al., Appl. Phys. Lett. 103 (2013), 071602

[2] V. Chobpattana et al., J. Appl. Phys. 114 (2013), 154108

[3] H. Chen et al., IEEE TED 59 (2012), 2383-2389

[4] Y. Yuan et al., IEEE TED 59 (2012), 2100-2106