Paper EM+AS+SS-MoA9
Self-aligned Vertical ZnO-based Circuits by Spatial ALD

Monday, October 19, 2015, 5:00 pm, Room 211A

Metal oxide thin-film transistors (TFTs) are becoming the mainstream for display backplanes. These TFTs are fabricated with traditional photolithographic techniques, typically on rigid substrates. In our lab, we explore approaches that are more “print-compatible”, with broad alignment tolerance and no small-gap mask features. We deposit zinc oxide (ZnO) semiconductors, aluminum oxide (Al₂O₃) dielectrics, and aluminum-doped zinc oxide conductors by the fast, atmospheric pressure, large-area-compatible, spatial atomic layer deposition (SALD) process. In addition to depositing good-quality thin-film transistor layers at temperatures at and below 200 °C, this process can work with a wide variety of rough and deformable substrates.

Here we describe vertical TFT and circuit architectures that unite process simplicity with high performance. The liberal design rules result from vertical transistors with self-aligned source and drain contacts that define the sub-micron channel length. Using 10-micron design rules for both the minimum line/space dimensions and for alignment tolerances, we have fabricated 9-stage ring oscillators with greater than 1 MHz oscillation frequency, at supply voltage below 6 V. Starting with a gate layer with a re-entrant profile on the edge, these devices use spatial ALD to conformally coat the Al₂O₃ gate dielectric and ZnO semiconductor, and a line-of-sight deposition process such as evaporation for the aluminum electrodes. Individual device characteristics as well as circuit performance will be discussed.