| AVS 61st International Symposium & Exhibition | |
| Selective Deposition as an Enabler of Self-Alignment Focus Topic | Wednesday Sessions |
| Session SD-WeM |
| Session: | Fundamentals of Selective Deposition |
| Presenter: | CarolynR. Ellinger, Eastman Kodak Company |
| Authors: | C.R. Ellinger, Eastman Kodak Company S.F. Nelson, Eastman Kodak Company |
| Correspondent: | Click to Email |
In this talk we will review our current understanding of the process space of spatial ALD and selective area deposition – including ALD cycle time, process temperature, precursors and choice of inhibitor. Data will be presented on inhibition of the precursors useful for making all of the layers necessary for thin film transistors over a temperature range of 100°C to 250°C, namely DEZ, DMAI, and H2O. Our devices are composed of conductive aluminum-doped ZnO (AZO), semiconducting ZnO, and electrically insulating aluminum oxide.
We use selective area deposition as an alternative approach to printed electronics. We print an inhibiting polymer ink, and deposit active materials via spatial atomic layer deposition (ALD), thereby separating the ink requirements from the active materials requirements. We have previously shown a process flow using this methodology to make simple bottom gate ZnO thin film transistors (TFTs) that have the same device performance as TFTs using the same materials but patterned by more conventional photolithographic means. Here, we will present new data highlighting the advantages of the additive patterning allowed by selective area deposition. We demonstrate devices having architectures that are easily achievable with this approach, that are correspondingly difficult to achieve through subtractive processing methods.
In addition to providing design freedom, the patterned-by-printing process flow allows for high throughput and fast process speeds. The atmospheric spatial ALD system enables the use of very short cycle times, with single gas exposure times between 25 and 200 ms (cycle times of 100 to 800 ms). In addition, since there is no time penalty for pumping down a reaction chamber to vacuum levels, the process time is approximately the number of cycles required times the cycle time. Additional gains in process speed are to be had by using selective area deposition and printing, because there are no inorganic etch steps and no need for exposure or development of a photoresist. The process time is simply determined by the print rate and the time necessary to remove the inhibitor at the end of spatial ALD deposition. For our typical conditions, we complete a full pattern process cycle in less than 20 minutes, and can build functional circuits only hours after completing the layout of a new design. These studies show that the patterned-by-printing method offers a rapid cycle time approach to high quality electronics on a variety of supports.