| AVS 61st International Symposium & Exhibition | |
| Selective Deposition as an Enabler of Self-Alignment Focus Topic | Wednesday Sessions |
| Session SD-WeA |
| Session: | Process Development for Selective Deposition and Self-Aligned Patterning |
| Presenter: | Andrew Simon, IBM Microelectronics Division |
| Authors: | A.H. Simon, IBM Microelectronics Division T. Bolom, GLOBALFOUNDRIES Inc. C. Niu, ST Microelectronics F.H. Baumann, IBM Microelectronics Division C.-K. Hu, IBM Research Division C. Parks, IBM Microelectronics Division J. Nag, IBM Microelectronics Division J.-Y. Lee, GLOBALFOUNDRIES Inc. C.-C. Yang, IBM Research Division S. Nguyen, IBM Research Division D. Priyadarshini, IBM Microelectronics Division D. Kioussis, IBM Microelectronics Division T. Nogami, IBM Research Division S. Guggilla, Applied Materials, Inc. J. Ren, Applied Materials, Inc. J. AuBuchon, Applied Materials, Inc. |
| Correspondent: | Click to Email |
A key requirement in scaling of Cu interconnects to groundrules at 14nm is maintaining electromigration (EM) performance. Adhesion of the Cu to the capping layer is a major reliability limitation, and adhesion-promotion schemes involving self-segregation of alloy components (e.g., Al, Mn) and selective metal capping (most often Co) have been developed. A parallel development is the use of seed-enhancement liner layers, (e.g. CVD Co), to improve conformality and Cu wettability while maintaining compatibility with established polishing processes. In this study, we compare the EM performance of CuMn self-capping to selective CVD Co capping on 22nm-Groundrule Cu interconnects, with and without the use of a CVD Co seed-enhancement layer.
Dual-damascene 22nm-groundrule interconnects were etched in a k=2.5 dielectric. Deposition of the PVD Ta(N) barrier, CVD Co liner layer and PVD Cu or CuMn seed layers was done on a clustered mainframe. After plating and CMP, capping was done either with SiCxNyHz alone, or with selective CVD-Co followed by SiCxNyHz.
SIMS studies [1] comparing Mn-depth profiles of CuMn-seeded samples with a PVD Ta(N)-only liner vs a Ta(N)/CVD Co liner were done on wires capped only with SiCxNyHz. The PVD TaN/Ta liner shows a spike in Mn-concentration at the cap-layer interface of ~8e20 atoms/cm3, consistent with enhanced EM. In contrast, the CVD Co seed-enhancement layer results in a ~5x suppression of Mn self-capping due to the presence of the carbonyl CVD Co layer (Fig.1).
Further studies compared PVD TaN/Ta liner / CuMn seed samples vs. selective CVD Co capped-samples with either (a) PVD TaN/Ta / Cu seed -or- (b) PVD Ta(N) / CVD Co-liner / PVD Cu liner/seed schemes. Fig. 2 shows TEM/EDX images of selective-CVD Co capped samples with both PVD Ta(N)-only or PVD Ta(N) / CVD Co liners. The full-encapsulation of the Cu wire with the CVD Co liner and selective CVD Co cap is apparent in the lower-right EDX image, with strong Co signals around the entire periphery. In contrast, the sample with Co only in the selective capping layer (upper right) shows a strong Co signal only in the cap layer.
Median downstream EM lifetimes at 300C for PVD Ta(N)/ Liners with either Co caps or CuMn seedlayers were in the range of 15-40 hours (Fig.3), consistent with previously-reported activation energies of 1.0eV[2]. However, the CVD Co Liner / selective Co cap samples showed median failure times of >150 hours at 400C and >3000 hours at 340C (Fig. 4), indicating an exceptionally high activation energy of 1.7 eV. Acknowledgements: This work was performed by the Research and Development Alliance Teams at various IBM Research and Development Facilities