AVS 61st International Symposium & Exhibition
    Plasma Science and Technology Tuesday Sessions
       Session PS-TuA

Paper PS-TuA8
Contact Level Patterning Challenges for Sub 22-nm Architecture

Tuesday, November 11, 2014, 4:40 pm, Room 308

Session: Advanced BEOL/Interconnect Etching
Presenter: Jeffrey Shearer, IBM Corporation
Authors: J.C. Shearer, IBM Corporation
J. Dechene, IBM Corporation
S. Kanakasabapathy, IBM Corporation
N. Mohanty, TEL Technology Center, America, LLC
B. Messer, TEL Technology Center, America, LLC
H. Cottle, TEL Technology Center, America, LLC
A. Metz, TEL Technology Center, America, LLC
J. Lee, Samsung Electronics
Correspondent: Click to Email
As gate pitch scaling continues past the 22nm node, we are approaching gate and contact pitches below the threshold of single-exposed lithography. One has to decompose the contact layer into multiple reticles and integrate them on the wafer to achieve an effective pitch less than this threshold. Such integration schemes bring with them issues with substrate damage and gate-contact shorts. Although exercised in BEOL patterning schemes, multicolor integration schemes require customization for the contact module. Damage from plasma exposure to the gate sidewall and source/drain in multiple color integration schemes can detract from gate to contact short yield and device yield. This paper will present innovative etch-integration cooptimization options to minimize plasma induced damage. We also highlight the process challenges in pattern fidelity that the industry has to surmount to make these manufacturable as well as RIE strategies that will help overcome these challenges. Hard mask memorization will be discussed for contact level integration as well as how material selection and etch process optimizations are needed to ensure pattern robustness. Specifically, data will show that multicolor processing causes earlier colors to have degraded device performance. A metal hard mask memorization scheme will be discussed as a way to alleviate multiple source/drain plasma exposures during product processing, thereby improving device yield.