| AVS 61st International Symposium & Exhibition | |
| Manufacturing Science and Technology | Thursday Sessions |
| Session MS-ThP |
| Session: | Manufacturing Science and Technology Poster Session |
| Presenter: | ShihChun Tsai, United Microelectronics Corporation, Taiwan, Republic of China |
| Correspondent: | Click to Email |
Double patterning lithography (DPL)
technologies have become a must for 32nm
nodes below. Currently have 2 approaches for DPL:
Self-aligned double patterning(SADP) and litho
etch litho etch(LELE).In this paper, we focus on
LELE induce issue, and present an etching solution
to solve this critical VIA open issue.