Paper MN+NS-TuA3
Fabrication and Electrical Performance of Through Silicon Via Interconnects Filled with a Copper/Carbon Nanotube Composite

Tuesday, November 11, 2014, 3:00 pm, Room 301

Three-dimensional integrated circuit (3D-IC) technology has been developed using copper (Cu) filled through silicon vias (TSVs). The vertical interconnects pass through a set of stacked die and enable many applications that benefit from increased bandwidth, reduced signal delay, and improved power management. However, the reliability of Cu interconnects is a serious concern since the performance is affected by electromigration and stress associated with mismatch in thermal expansion coefficients. Carbon nanotubes (CNTs) are nanoscale materials which possess a high Young's modulus, a low coefficient of thermal expansion, and high thermal conductivity. Compared to Cu, CNTs exhibit low resistivity due to the existence of ballistic conduction and they are capable of carrying a higher current density. In this work, we fabricated TSVs using a novel materials system consisting of a composite of Cu and CNTs as a possible solution to the problems encountered in Cu-based interconnects. First, blind TSVs were fabricated using a Bosch process. After etching, an insulating layer, a metallic seed layer, and a catalyst layer were deposited previous to CNT growth. Vertically aligned CNTs were grown by chemical vapor deposition method. Finally, Cu was deposited by periodic reverse pulse electroplating inside the vias to form a Cu/CNT composite. Polishing completed the fabrication and allowed measurement of electrical performance for TSV interconnects. The experimental results were compared for interconnects filled with Cu and those filled with the Cu/CNT composite. The results are encouraging for the Cu/CNT composite having potential application as a TSV interconnect material.