Imaging of the native inversion layer on Silicon-on-Insulator via Scanning Surface Photovoltage;

Implications for RF harmonic generation

Daminda Dahanayaka¹, Andrew Wong², Phil Kaszuba¹, Leon Moszkowicz¹, Randall Wells¹, Frank Alwine¹, Lloyd A. Bumm³, Richard Phelps¹ and James Slinkman¹

¹IBM Microelectronics, 1000 River Street, Essex Junction, Vermont 05452

²Thayer School of Engineering, Dartmouth College, 14 Engineering Drive, Hanover, NH 03755

³Homer L DodgeDepartment of Physics and Astronomy, University of Oklahoma, 440 W. Brooks Street, Norman, OK 73019

Email: damindahd@us.ibm.com

One of the major challenges encountered during the development of IBM’s state-of-the-art RF CMOS Technology on Silicon-on-Insulator (SOI) was to overcome the adverse effects on the harmonic performance of stacked switch devices and transmission lines due to the presence of trapped positive charge, Q⁺, at the interface of the buried oxide (BOX) and the underlying high-resistivity substrate (SX). Most commercially available standard SOI substrates for RF applications have specifications to maintain Q⁺ less than 10¹¹ cm^-2. The substrate resistivity for IBMs technology is specified to be greater than 1000 ohm-cm, (p-type), i.e. p₀ ≈ 5 x 10¹³ cm^-3. This combination induces a “built-in” n-type inversion layer just under the BOX/SX interface. Using “Scanning Surface Photovoltage” (SSPV) microscopy, we present the first data to show quantitatively the extent of this inversion layer into the substrate. The technique disclosed here quantifies the inversion layer, the degree to which it can be suppressed, and has led to further enhancements to the RF technology on SOI, such as substantial NFET off-state leakage reduction.