| AVS 61st International Symposium & Exhibition | |
| Energy Frontiers Focus Topic | Tuesday Sessions |
| Session EN-TuP |
| Session: | Energy Frontiers Poster Session |
| Presenter: | Gilad Zorn, GE Global Research Center |
| Authors: | G. Zorn, GE Global Research Center B.A. Korevaar, GE Global Research Center J.R. Cournoyer, GE Global Research Center K. Dovidenko, GE Global Research Center |
| Correspondent: | Click to Email |
Scanning capacitance microscopy (SCM) is a powerful method for mapping dopant variation in semi-conductor and PV devices. In SCM a conducting AFM tip is used to scan the surface in contact mode. The tip and sample surface form a metal–insulator–semiconductor structure. Simultaneous with the topography data collection, an AC bias is applied to the sample while the tip is grounded. The resulting oscillation of carriers near the tip, leads to a modulated capacitance (dC/dV), which is measured by a capacitance-sensing circuit. The capacitance measured by the SCM sensor varies as the carriers move towards (accumulation) and away from (depletion) the probe. When the sample is fully depleted the measured capacitance is that of the oxide plus the depletion layer. When carriers are accumulated at the surface, the measured capacitance is that of the oxide layer. The magnitude of the change in capacitance (dC) for a given change in voltage (dV)depends on the carrier concentration. For heavily doped materials the carriers do not move far. Hence, the measured capacitance variation between accumulation and depletion is small. The opposite is true for lightly doped semiconductors which yield a large capacitance change. The sign of the measured dC/dV signal changes between n-type and p-type. In p-type semiconductors, as the sample voltage becomes more negative relative to the tip, the width of the surface depletion layer will increase. Hence, the total capacitance will decrease. If the sample voltage is positive, accumulation will occur, and the capacitance measured will be that of the oxide layer only. For n-type samples the effects are opposite.
This work describes SCM cross-sectional mapping of CdTe devices, focusing on the role of the various processing steps during the device fabrication. These steps include CdTe deposition, CdCl2-treatment, and a copper-step. Generally it is accepted within the CdTe community that as deposited CdTe is lightly doped and could be both n-type or p-type depending on the deposition temperature and process. The effect of the CdCl2 treatment is typically presented as a way to create so-called A-centers, which dope the CdTe p-type. The final copper-step then fills the A-centers and creates Cu on Cd-sites, which further dopes the CdTe p-type to levels in the range of 5x1013 to 5x1014 cm-3. Here SCM is used to demonstrate the role of the various processing steps with regards to carrier density. SCM dopant map could clearly distinguish n and p-type CdTe as well as the p-n transition across the interface. It was found that the doping distribution across the CdTe layer depends on the type of the copper treatment.