| AVS 61st International Symposium & Exhibition | |
| Electronic Materials and Processing | Tuesday Sessions |
| Session EM-TuM |
| Session: | Advanced Interconnects and Materials |
| Presenter: | Jean-Francois de Marneffe, IMEC, Belgium |
| Authors: | J.-F. de Marneffe, IMEC, Belgium L. Zhang, IMEC, KU Leuven, Belgium M.H. Heyne, IMEC, KU Leuven, Belgium M. Krishtab, IMEC, KU Leuven, Belgium A. Goodyear, Oxford Instruments Plasma Technologies M. Cooke, Oxford Instruments Plasma Technologies N. Heylen, IMEC, Belgium I. Ciofi, IMEC, Belgium L.G. Wen, IMEC, Belgium C.J. Wilson, IMEC, Belgium V. Rutigliani, University Bari, Italy S. Decoster, IMEC, Belgium T. Savage, SBA Materials, Inc. K. Matsunaga, Tokyo Electron Kyushu Limited, Japan K. Nafus, Tokyo Electron Kyushu Limited, Japan J. Boemmels, IMEC, Belgium Z. Tokei, IMEC, Belgium M. Baklanov, IMEC, Belgium |
| Correspondent: | Click to Email |
In recent year, two innovative strategies have been proposed to decrease plasma-induced low-k damage: the P4 approach [Frot et al., 2011] and the cryogenic etch approach [Zhang et al., 2013]. The P4 or “pore stuffing” uses an extrinsic sacrificial pore filler, allowing protection during plasma etching and metallization steps. The cryogenic etch is based on in-situ pore filling by etch byproducts and/or SiOFx sidewall passivation.
In this work, a PMO spin-on material with pristine k = 2.31 from SBA has been integrated on 300mm wafers. The integration vehicle uses narrow-spacing structures, i.e. 30nm low-k lines at 180nm pitch.
For the cryogenic etch approach, after lithography, the SiC/SOC/SOG hardmask is trimmed and opened using standard etch. Low-k etching is performed by means of a SF6-based plasma chemistry in an ICP chamber equipped with a liquid-N2 cooled substrate holder set at a base temperature of -120°C. Careful optimization of etch conditions allows to considerably decrease the loss of Si-CH3 bonds, keeping an acceptable etch rate, good hardmask selectivity, and reduced bottom roughness. After patterning and subsequent byproduct removal by annealing, a conventional Cu metallization is performed using TaNTa barrier, Cu seed and electroplating. After chemical-mechanical polishing (CMP) and SiC passivation, functional circuits gave integrated dielectric constant of kint = 2.38, i.e. showing a Δk = 0.07 relative to pristine.
For the pore stuffing approach, PMMA was used as filling material and driven in after low-k deposition. Due to thermal instability of PMMA, a low-temperature Si3N4 hardmask was used, as well as low-temperature TaNTa barrier. PMMA was removed after CMP, by means of He-H2 downstream plasma ashing or thermal decomposition. Functional circuits gave integrated dielectric constants kint = 2.73 (thermal unstuffing) and kint = 3.14 (He-H2 ashing).
By comparison of both approaches, it is observed that pore stuffing increases interconnect flow complexity, by the addition of stuffing and unstuffing steps which can also damage the low-k material; however post-etch surfaces are smooth and barrier metal penetration is suppressed. The pore stuffing approach could be improved by using more thermally stable polymers and the search for damage-free unstuffing methods. The current cryogenic etch process requires only minor changes into the process flow, however currently it requires a base temperature of -120°C. The cryogenic etch process could be improved by the use of plasma additives enhancing by-products condensation and/or pre-condensation steps. We acknowledge support from the European Union under grant agreement No. 318804 (SNM).