AVS 61st International Symposium & Exhibition
    2D Materials Focus Topic Thursday Sessions
       Session 2D-ThP

Paper 2D-ThP17
Development of Low-k Dielectric for Graphene device

Thursday, November 13, 2014, 6:00 pm, Room Hall D

Session: 2D Materials Poster Session
Presenter: YoungGon Lee, University of Texas at Dallas
Authors: Y.G. Lee, University of Texas at Dallas
L. Cheng, University of Texas at Dallas
Y. Kim, Gwangju Institute of Science and Technology
G. Mordi, Samsung
HH. Hwang, University of Texas at Dallas
A. Lucero, University of Texas at Dallas
BH. Lee, Gwangju Institute of Science and Technology
J. Kim, University of Texas at Dallas
Correspondent: Click to Email
Graphene bilayer pseudo-spin field effect transistor (BiSFET) has been suggested as one of the most promising nanoelectronics since it has a lot of advantages such as low power operation and good scalability.[1] For graphene based 2D devices like BiSFET, it is preferable to have an extremely thin insulator layer with a low-k dielectric constant conformally deposited on the graphene surface. In this work, the transport behavior of non 2D crystalline low-k dielectrics, 3,4,9,10-parylene tetracarboxylic dianhydride (PTCDA), has been investigated to apply the graphene based device as an interlayer tunnel barrier for BiSFET. PTCDA thin films were evaporated on highly ordered pyrolytic graphite (HOPG) and Si surfaces using the molecular beam deposition. Then, Ru/Al was deposited using E-beam evaporator for electrical measurement.

PTCDA devices grown on Si substrate exhibit a rectifying behavior because Schottky can be formed at interface between PTCDA layer and Si substrate. The dielectric constants around ~1.6 - 2.2 were extracted from capacitance at built-in potential. These results are consistent with previous papers about organic-inorganic Schottky diode.[2] However, as the PTCDA film thickness is scaled down from 20 to 5 nm, the reverse currents increase up to six orders of magnitude possibly because of the tunneling current. In order to explore the tunneling behavior of PTCDA layer on the graphene, the current behaviors of PTCDA layer on HOPG has been investigated. Similar to the current behavior of thin PTCDA layer on Si substrate, PTCDA device on HOPG exhibit tunneling behavior; the current increase linearly with the applied bias in low bias region, whereas it changes exponentially as a function of applied bias in high bias region. The tunneling current of PTCDA layer shows thickness dependence. These behaviors can be modeled by direct tunneling equation. [3] Capacitances around ~9 and ~16 pF in 3 and 1 nm PTCDA layer on HOPG, respectively, were identified using a time domain reflectometry (TDR) measurement, which are coincide with the value of PTCDA on Si substrate. In addition, there is a weak temperature dependence in current of thin PTCDA device.

In summary, non-2D crystalline low-k dielectric has been developed for the tunnel barrier of graphene based device. The thickness of PTCDA film was successfully scaled down to a few layers. It has also demonstrated that the devices fabricated with thin PTCDA films on HOPG exhibit feasibility of direct tunneling behaviors.

[1] S. K. Banerjee et al., Electron Device Lett. 30, 158 (2009).

[2] S. R. Forrest et al., J. Appl. Phys. 56, 543 (1984).

[3] W. Wang et al., Rep. Prog. Phys. 68, 523 (2005).