AVS 60th International Symposium and Exhibition
    Manufacturing Science and Technology Tuesday Sessions
       Session MS+AS+EL+EM+PS+TF-TuA

Paper MS+AS+EL+EM+PS+TF-TuA4
DSA Patterning for sub-40 nm Pitch Features

Tuesday, October 29, 2013, 3:00 pm, Room 202 B

Session: Manufacturing Challenges of Nanoscale Patterning
Presenter: I.C. Estrada-Raygoza, IBM Albany Nanotech Center
Authors: I.C. Estrada-Raygoza, IBM Albany Nanotech Center
C. Liu, IBM Albany Nanotech Center
Y. Yin, IBM Albany Nanotech Center
J. Abdallah, IBM Albany Nanotech Center
S. Mignot, GLOBALFOUNDRIES U.S. Inc.
B.G. Morris, IBM Albany Nanotech Center
M.E. Colburn, IBM Albany Nanotech Center
V. Rastogi, TEL Technology Center, America, LLC
N. Mohanti, TEL Technology Center, America, LLC
A. Raley, TEL Technology Center, America, LLC
A. Ko, TEL Technology Center, America, LLC
Correspondent: Click to Email
As the semiconductor industry targets sub-40 nm pitch features, there will be a necessity for new patterning techniques which allow for the extension beyond single ArF-immersion patterning capability of 38 half pitch features. To meet today’s aggressive design requirements, double patterning techniques, such as Pitch Splitting (PS) Lithography and Sidewall Image Transfer (SIT), have been widely used. Below 38 nm pitch design the industry has looked toward Extreme Ultraviolet (EUV), Double Sidewall Image Transfer (SIT2) and Directed Self-Assembly (DSA) as strong emerging candidates. A major component to the success of the DSA technique is the development of effective etch processes. This talk targets to discuss the challenges and innovations of the plasma etch process on sub-40 nm pitch features produced by DSA chemo and grapho-epitaxy guiding patterns. Each DSA scheme presents different challenges, depending of the aspect ratio, density of the patterns and etch stack materials, but in general, the parameters that have been studied are selectivity to both masking and etched materials, across wafer profile uniformity, critical dimension (CD) uniformity and line-edge/line-width roughness (LER/LWR). This work was performed by the Research Alliance Teams at Albany IBM Research and Development Facilities.