AVS 60th International Symposium and Exhibition
    Electronic Materials and Processing Monday Sessions
       Session EM+TF-MoM

Invited Paper EM+TF-MoM8
Challenges and Progress in Complementary Tunnel FETs

Monday, October 28, 2013, 10:40 am, Room 101 B

Session: High-k Gate Oxides for High Mobility Semiconductors I
Presenter: M. Wistey, University of Notre Dame
Authors: M. Wistey, University of Notre Dame
G. Zhou, University of Notre Dame
Y. Lu, University of Notre Dame
R. Li, University of Notre Dame
Q. Zhang, University of Notre Dame
W.S. Hwang, University of Notre Dame
Q. Liu, University of Notre Dame
T. Vasen, University of Notre Dame
C. Chen, University of Notre Dame
M. Qi, University of Notre Dame
H. Zhu, University of Notre Dame
J.-M. Kuo, University of Notre Dame
S. Chae, University of Notre Dame
Y. Lu, University of Notre Dame
H. Zhu, University of Notre Dame
J.-M. Kuo, University of Notre Dame
T. Kosel, University of Notre Dame
S. Koswatta, University of Notre Dame
P.J. Fay, University of Notre Dame
A. Seabaugh, University of Notre Dame
H. Xing, University of Notre Dame
Correspondent: Click to Email
Tunneling field effect transistors (TFETs) may offer logic performance comparable with low-power CMOS while consuming far less power. This talk summarizes recent work on TFETs based on III-V and 2D materials. In this talk , we discuss recent results in modeling and fabrication of TFETs with high on current, low off current, and low subthreshold swing (SS). Self-aligned, planar III-V TFETs are shown with high on-current of ION=0.18mA/µm at VGS=0.5 V. An analytic and simulation model was developed to compare between in-line (vertical) and transverse tunneling geometries, as well as to compare the supply voltage, bandgap, SS and Ion for single-gate, double-gate, and gate-all-around (nanowire) geometries. The optimal bandgap was found to depend on device geometry and size, leading to possible variability between devices. Also, for gate lengths below 10 nm, the minimum VDD for planar TFETs increases to 4.8 V, reducing the advantage over MOSFETs. But GAA and 2D materials still offer VDD as low as 0.22 V with ION/IOFF=105. As with MOSFETs, gate dielectrics play a predominant role in performance. High Dit easily hinders device performance and requires SS above 60 mV/decade. Test dielectric interfaces with strained InP and InAs/ZnTe interfaces were studied for low-voltage applications. Models and experiments both showed that TFETs are sensitive to fabrication misalignment in the gate overlap regions. Self-aligned devices show the best performance and highest yield. Finally, to replace CMOS, we need an inverter with low static power dissipation. This requires complementary devices analogous to NMOS and PMOS. The talk discusses some of the lessons from the previous work for moving forward with pTFETs.