Invited Paper NM+NS+MS+EM-MoA10
Solution Based Processing of Floating Gate Memory using Additive-Driven Self-Assembly and Nanoimprint Lithography

Monday, October 29, 2012, 5:00 pm, Room 16

Polymer and polymer-inorganic hybrid materials organized at the nanoscale are at the heart of many devices that can be created on flexible substrates for applications in energy generation and storage, microelectronics, optoelectronics, communications and sensors. The challenge is to produce these materials using process platforms and materials sets that are environmentally and economically sustainable and can be scaled for cost-effective, high value-added manufacturing. Here we describe a resource efficient, additive approach based on roll-to-roll coating of self-assembled hybrid materials. Specifically we report that nanostructured templates with periodic spherical, cylindrical, and lamellar morphologies exhibiting sub-10 nm domains can be easily obtained through the blending of commercially available disordered polymer surfactants with commodity homopolymers that selectively associate with one segment of the surfactant. We further demonstrate that order in the surfactant systems and in block copolymer templates can be induced by nanoparticle additives that undergo multi-point hydrogen bonding with one of the segments of the polymer template. These additives, which include metal and semiconducting nanoparticles, fullerenes, and other active components, impart functionality to the device. The strong interactions further enable particle loadings of more than 40% in the target phase, resolving a crucial constraint for many applications. These systems can be scaled in our newly constructed R2R processing facility, which includes a custom microgravure coater for hybrid materials that is equipped for in-line substrate planarization and a precision R2R UV-assisted nanoimprint lithography (NIL) tool.

We illustrate the capabilities of these approaches by the fabrication of floating gate field effect transistor memory devices. For this application, the charge trapping layer is comprised of well-ordered polymer/gold NP composites prepared via additive-driven self-assembly; the addition of gold nanoparticles that selectively hydrogen bond with pyridine in poly(styrene-b-2-vinyl pyridine) copolymers yields well-ordered hybrid materials at gold nanoparticle loadings of more than 40 wt.%. The charge trapping layer is sandwiched between a dielectric layer and a poly(3-hexylthiophene) semiconductor layer. We can achieve facile control of the memory windows by changing the density of gold nanoparticles. The devices show high carrier mobility (> 0.1 cm²/Vs), controllable memory windows (0~50V), high on/off ratio (>10⁵) between memory states and long retention times. Strategies for patterning of the device using NIL will be discussed.