AVS 59th Annual International Symposium and Exhibition
    Graphene and Related Materials Focus Topic Monday Sessions
       Session GR+EM+NS+PS+SS+TF-MoM

Paper GR+EM+NS+PS+SS+TF-MoM11
Three-Dimensional Graphene Architecture Growth and Its Facile Transfer to Three-Dimensional Substrates

Monday, October 29, 2012, 11:40 am, Room 13

Session: Graphene Growth
Presenter: J.-H. Park, Sungkyunkwan University, Republic of Korea
Authors: J.-H. Park, Sungkyunkwan University, Republic of Korea
H.-J. Shin, Samsung Advanced Institute of Technology, Republic of Korea
J.Y. Choi, Samsung Advanced Institute of Technology, Republic of Korea
J.R. Ahn, Sungkyunkwan University, Republic of Korea
Correspondent: Click to Email
Recent development of large area graphene synthesis on metal layer by chemical vapor deposition (CVD) or epitaxial growth on silicon carbide (SiC) opened the possibility for applications such as transparent electrodes for ITO replacement. For instance, graphene has been demonstrated for use in a liquid crystal display (LCD) and/or organic light emitting diode (OLED) test cell as a bottom electrode. However, the actual device, e.g., an active-matrix (AM) LCD, operates by switching individual elements of a display, using a thin-film transistor (TFT) for each pixel. Here, the pixel electrode of a display should extend down to the transistor’s source or drain, thereby making contact with a via hole, which demands that a three-dimensional (3D) architecture electrode be deposited on a flat surface as well as its side walls. Although large-area graphene growth can be applied for a wide range of applications, 3D graphene architecture growth has not been realized for actual devices due to the original limitation of planar graphene growth. Herein, we demonstrate for the first time 3D graphene architecture growth and its facile transfer to a planar and/or 3D substrate. To prevent agglomeration of nano-scale metal catalyst by the CVD process, we chose a SiC system. Graphene, a few layers thick, was epitaxially grown on a pre-patterned SiC substrate with nano-size thickness which was produced by photolithography and dry etching. Graphene on a vertical facet of the SiC pattern with a few-hundred nanometers in height was perfectly prepared using this approach, contrary to the CVD method. Furthermore, we suggest the use of a facile transfer method of graphene on SiC to a SiO2 substrate using thermal release tape after hydrogen intercalation. In spite of the troublesome transfer issue of SiC, the geometry of the 3D graphene was perfectly transferred onto the planar SiO2 as well as the 3D SiO2 structure. In other words, the 3D graphene architecture was maintained as a floating cap structure on planar SiO2 and the vertical facet of the 3D SiO2 structure was well covered. Moreover, the graphene bottom layer without a 3D cap and the inverted bowl structure in the 3D graphene architecture were selectivly transferred by controlling intercalation and pressure. These approaches could provide a beneficial method for preparing a 3D graphene architecture as well as for modifying the ordered structure to be utilized in real devices.