| AVS 59th Annual International Symposium and Exhibition | |
| Graphene and Related Materials Focus Topic | Thursday Sessions |
| Session GR+AS+NS+SS-ThM |
| Session: | Graphene Nanostructures |
| Presenter: | M. Schroter, Technische Universität Dresden, Germany |
| Authors: | P. Sakalas, Technische Universität Dresden, Germany M. Schroter, Technische Universität Dresden, Germany |
| Correspondent: | Click to Email |
CNTFETs with a single semiconducting tube yield too low current (25 µA) for useful applications and thus the transistors with thousands tubes in parallel are being fabricated [1][2]. unfortunately, following theory 1/3rd of all tubes are metallic. Carrier scattering is better understood for metallic tubes and it is believed that for semiconducting tubes, despite more complexity, the same scattering mechanisms are applicable: CNTs defect scattering, physical bends and phonon scattering are present. Investigation of CNTFETs with a single semicoducting (ST), single metallic (MT) and metallic+semiconducting (MST) tubes at different lattice temperature environment was never done before and enables a deeper insight of CNT transport properties to further improve the application-oriented device behavior. It was shown that multifinger CNTFETs exhibited a weak temperature dependence of IV, RF and NF indicating a very weak electron-phonon interaction and the absence of charge-carrier freeze-out known for conventional doped semiconductors [3],[4].
In this work transistors with single ST, single MT and double MST were selected. Transistors have 800 nm channel length and features n-type behavior. IV characteristics were measured on wafer for manufacturable CNTFET process selected single CNTs at different lattice temperatures. The investigated structures have a fixed gate length of 0.35 µm and gate width of 40 µm. The source-drain spacing (channel length) is 800 nm. A 20 nm thick HfO2 was used for the gate oxide. The devices were fabricated with the process technology described in [1][2].The CNTFETs were embedded in DC pads for on-wafer measurements. Transfer characteristics of ST and MT transistor structures at ambient temperature T0 = 300 K, are shown in Fig.1 and Fig.2, Fig.3, Fig.4. The drain current show saturation for ST device, typical for MOSFETs. Nevertheless the carrier transport is very different. The dependence of drain current over the temperature will enable the analysis of transport behavior of single ST and MT and coupled MST. As it is seen from Fig.3 and Fig.4 the MT transistor structure behaves as nonlinear resistor.