Invited Paper EM+TF+OX+GR-MoM10
Passivation of Interfacial Defects in GaAs and Other III-Vs

Monday, October 29, 2012, 11:20 am, Room 009

It has always been harder to make FETs from GaAs than Si, because of ‘Fermi level pinning’ and the difficulty of passivating its surfaces. These issues were discussed by Spicer et al [1] in the ‘unified defect model’ and Hasegawa [2] is his ‘Disorder Induced Gap states’ model. Since 1997 it was possible to make inverted GaAs MOSFETs using the epitaxial Gadolinium gallium oxide [3]. The main impetuous now is to use atomic layer deposition (ALD) to make scalable FETs [4], as recently achieved by Intel [5]. The obvious question is why (In)GaAs is much harder to passivate than Si. The early answer was its poor native oxide. But since the advent of good ALD HfO2 or Al2O3 oxides on Si, this answer is deficient, as they should also work on GaAs [6]. The underlying reason for defects is not stress, it must be chemical. I show that it arises from the polar bonding of GaAs [7], and a driving force to keep the surface Fermi level in a gap. The electron counting rule of Pashley [8] that describes surface reconstructions is shown to be a variant of auto-compensation, and it works more generally [9]. It leads to a continuous generation of defects if it is not satisfied. So the answer is to deposit oxide layers that meet this rule, and also to break any surface reconstructions that may lead to As-As dimers [9]. Diffusion barriers are also crucial to a good passivant, on GaAs or on Ge .

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2. H Hasegawa, et al, J Vac Sci Technol B 5 1097 (1987)

3. M Hong et al, Science 283 1897 (1997)

4. P D Ye et al, App Phys Lett 83 180 (2003)

5. M Radosavljevic, et al, Tech Digest IEDM (2009) p13.1

6. C Hinkle, et al, Curr Opin Solid State Mat Sci 15 188 (2011)

7. W Harrison, J Vac Sci Technol 16 1492 (1979)

8. M D Pashley, Phys Rev B 40 10481 (1989)

9. J Robertson, L Lin, App Phys Letts 99 222906 (2011); 98 082903 (2011)