Paper EM+MI-ThA1
Dislocation Compensation in Ungraded ZnS_ySe_1-y/GaAs (001) Heterostructures

Thursday, November 1, 2012, 2:00 pm, Room 009

Control of strain and dislocation dynamics are important in determining the performance and reliability of semiconductor devices such as light-emitting diodes and photo-detectors. Experimental studies of ZnS_ySe_1-y /GaAs (001) heterostructures show that a dislocation compensation mechanism is active in structures involving abrupt interfaces. This mechanism involves the bending over of threading dislocations associated with misfit segments of one sense by misfit dislocations having the opposite sense, and it allows removal of threading dislocations from device structures.

Semiconductor device structures may be designed to take advantage of the dislocation compensation with the aid of a dislocation dynamics model accounting for misfit-threading interactions. To develop such a model we studied strain relaxation in ZnSe/GaAs (001) and ZnS_ySe_1-y /GaAs (001) heterostructures to determine the kinetic material parameters associated with dislocation glide and multiplication. Based on these results and by including misfit-threading interactions we developed a dislocation dynamics model which predicts dislocation compensation in arbitrary ZnS_ySe_1-y /GaAs (001) heterostructures.

Whereas our previous experimental work involved graded structures, this work focuses on the study of theoretical heterostructures comprising a device layer (DL) of ZnS_ySe_1-y on a ungraded buffer layer (BL) of ZnS_ySe_1-y deposited on a GaAs (001) substrate. We show that for a given device layer thickness and compositional change at the buffer-device layer interface there exists an optimum thickness of the ungraded buffer layer where the mobile threading dislocation density can be removed entirely. The optimum buffer layer thickness decreases monotonically with the compositional difference between buffer and device layer.