| AVS 58th Annual International Symposium and Exhibition | |
| Thin Film Division | Thursday Sessions |
| Session TF1-ThM |
| Session: | Post-Deposition Processing and Characterization of Thin Films |
| Presenter: | Yue Kuo, Texas A&M University |
| Correspondent: | Click to Email |
Thermal annealing is a critical but often neglected step in semiconductor production. It has been routinely used to activate the ion implanted dopant and at the same time, to restore the single crystal structure. However, it is also a powerful tool in repairing damages in bulk films as well as at film-film interfaces, which are caused by the plasma-related deposition or etching process. In addition, the thermal annealing step can change film characteristics, which affects the subsequent process result. In this talk, the author will review some of his recent work related to thermal annealing, which involves three types of solid-state devices and thin films. First, an example on repairing the RIE damaged a-Si:H TFT with a low temperature thermal annealing process will be given. This step reduced defects in the bulk a-Si:H and SiNx layers as well as at the gate-dielectric interface. This result has been interpreted in all TFT LCD productions around the world. In the second example, it will be shown that the thermal annealing step changed the grain size of the sputter deposited copper thin film. It resulted in the change of the copper-Cl reaction mechanism and therefore, the copper consumption rate. This is critical to a new plasma-based copper etch process that has been interpreted in large-area TFT LCDs and BiCMOS chips. In the third example, it will be shown that the post deposition annealing (PDA) condition is the key to the realization of a new type of nonvolatile memory device, i.e., the nanocrystals embedded high-k capacitors or MOSFETs. Furthermore, an addition low temperature annealing step removed the defects generated in the gate and back-contact sputtering processes. In summary, the thermal annealing effects are non-negligible because they are directly involved in product reliability and yield.
(1) Y. Kuo, “TFT and ULSIC – Competition or Collaboration,” Jpn. J. Appl. Phys., 47(3), 1845-1852 (2007).
(2) G. Liu, Y. Kuo, S. Ahmed, D. N. Buckley, and T. Tanaka-Ahmed, “Grain Size Effect on Plasma-based Copper Etch Process,” J. Electrochem. Soc., 155(6) H432-H437 (2008).
(3) Y. Kuo, “Status Review of Nanocrystals Embedded High-K Nonvolatile Memories,” ECS Trans. 35(3), 13-31(2011).