Paper TF-MoM8
New Method to Produce High-Quality Epitaxial Ge on Si Using SiO₂-Lined Etch Pits and Epitaxial Lateral Overgrowth for III-V Multijunction Solar Cells

Monday, October 31, 2011, 10:40 am, Room 107

Integrating a high-quality layer of epitaxial Ge on Si has been a longstanding engineering challenge, despite its technological importance. The applications of Ge-on-Si include ‘virtual substrates’ for III-V multijunction solar cells, high-mobility field-effect transistors, and optical interconnects monolithically integrated with Si-based circuitry. The primary difficulties in achieving Ge films of sufficient quality stem from the lattice mismatch that leads to a large density (> 10⁹ cm^-2) of threading dislocations (TDs) and the thermal expansion coefficient mismatch between Ge and Si that leads to microcracks or delamination of Ge film upon cooling from growth to room temperature. Herein, we present a new method to reduce the TD density, using a minimal number of standard microfabrication steps. The method begins with growing a 500-nm-thick epitaxial Ge layer on Si. A post-growth anneal step leads to a TD density of approximately 5x10⁷ cm^-2, as revealed by plan-view transmission electron microscopy (TEM) and etch pit density (EPD) measurements. The close agreement between EPD measurements and TEM shows that the EPD measurements reliably decorate all TDs. Etch pits are created around the dislocation cores in the Ge film. A 15-nm-thick layer of SiO₂ is subsequently deposited on the etch-pit-decorated Ge film. A thin layer of polymethyl methacrylate is then spin-coated onto the sample, which fills the etch pits and planarizes the Ge surface. Next, a reactive ion etching step is used to remove the polymer and SiO₂ from the planar regions of the sample surface surrounding the etch pits. An O₂ plasma is then used to selectively remove the remaining polymer, so that SiO₂ remains only within the etch pits. Lastly, a second layer of Ge is selectively grown on the exposed Ge surface and laterally over the SiO₂-lined etch pits until a fully coalesced Ge film is created. A final polishing step produces an atomically flat continuous Ge film. Ensuing EPD measurements reveal that the density of twin defects and TDs in the upper Ge layer is approximately 1.7x10⁶ cm^-2, such that the overall defect density is reduced by a factor greater than 30 compared to that in the initial Ge layer. Both theoretical and experimental evidence suggest that the defect density in GaAs films on Ge/Si must be less than 2x10⁶ cm^-2 to have a minority carrier lifetime comparable to GaAs films grown on Ge and GaAs substrates. Therefore, our new method of using SiO₂-lined etch pits to block the propagation of TDs in Ge may finally lead to device quality III-V materials integrated on Si substrates.