Invited Paper NM+MN+MS+TF-TuM10
CMOS Density Scaling in Non-Planar Multi-Gate Devices: A Patterning Perspective

Tuesday, November 1, 2011, 11:00 am, Room 207

The use of planar Si CMOS device technology may continue beyond the 22 nm node. However, the requirements for the gate dielectric and junction depth needed to maintain control of short channel effects might prove to be unobtainable in devices scaled to meet the integration density requirements of the 14 nm node and beyond. Consequently, an additional method for improving the electrostatics of the device is required. This realization has driven a steady increase in research on non-planar multi-gate CMOS devices over the past 5 years. Raising the Si channel out of the plane of the substrate creates the opportunity to form the gate electrode around multiple sides of the channel. This geometry results in a superior situation from an electrostatics standpoint compared to a planar device where the gate electrode is present only on the top surface of the channel.

In this talk, we will discuss the challenges of fabricating three non-planar multi-gate devices from Si on insulator (SOI) substrates: (1) the FinFET, where the gate controls two sides of a thin Si mesa or fin (2) the Trigate where the gate controls three sides of a Si fin and (3) a gate-all-around nanowire transistor where the gate electrode surrounds all sides of a suspended Si channel. We will present experimental results from advanced prototypes of these devices fabricated at dimensions and densities relevant to 14 and 10 nm node technology. An emphasis will be give to the unique role lithography and patterning play in determining the electrical behavior of these devices. These results offer insight into what may lie ahead for Si CMOS scaling and how it will impact the demands placed on patterning and metrology.