AVS 57th International Symposium & Exhibition
    MEMS and NEMS Thursday Sessions
       Session MN-ThP

Paper MN-ThP8
Development of High-Density Cylindrical Ion Trap Array for Mass Spectrometer

Thursday, October 21, 2010, 6:00 pm, Room Southwest Exhibit Hall

Session: MEMS and NEMS Poster Session
Presenter: T. Wu, University of South Florida
Authors: T. Wu, University of South Florida
A. Chaudhary, University of South Florida
F. Amerom, University of South Florida
T. Short, University of South Florida
J. Wang, University of South Florida
Correspondent: Click to Email

This paper presents the development of high-density cylindrical ion trap array for mass spectrometer (CIT-MS).The previous research has mainly focused on the adjusting the ring electrode radius r0, cylinder length z0, and endplate hole electrode rH (Figure 1) and developing a fabrication process involving a back-to-back bonding of two half CIT structures. However, recently it has been noticed that a key factor that limits the performance of the CIT is the high capacitance between endplate electrodes and ring electrode due to the small gap; besides, the back-to-back bonding of two half structures could bring a maximum 5 micron misalignment. Based on these concerns, a new geometry of CIT array for mass spectrometer has been designed; also a new fabrication process has been developed accordingly.

In the newly developed generation of CIT-MS, the geometry design of CIT has been focusing on increasing the gap between the ring electrode and endplate electrode. Several simulations have been done on this subject. Other important improvements include better ring-to-endplate aperture alignment using dedicated alignment marks during flip-chip bonding, hexagonal orientation of traps leading to smaller pitch between each trap to increase density (thereby more trapping volume per unit area of wafer), larger vacuum gaps for operation at higher voltages for increased mass range and selective metallization using lithography techniques to reduce the overlap area of ring and endplate electrodes for lower capacitance.

A new fabrication process has been designed to achieve the improvements mentioned above. A suspended endplate electrode structure, using KOH/DRIE etching techniques, was used to increase the gap and reduce the overlapping area at the same time. To avoid surface charging of the dielectric surface that is exposed to ions, Atomic Layer Deposition (ALD) was investigated to deposit highly resistive (ZnO) layer on the dielectric surface to dissipate charge, while adding minimum to the capacitance. Flip-chip bonding was used to bond the ring-electrode and endplate electrodes and minimize the misalignment between the two substrates. With these considerations, both the esolution specificity and sensitivity are expected to improve. The design of optical mask for this process is underway and we report preliminary progress based on the latest findings.