Paper LB-WeA1
Studying Low-Resistance Silicide Contacts using Atom-Probe Tomography

Wednesday, October 20, 2010, 2:00 pm, Room Cimmaron

Improvements in energy efficiency of electronic devices are receiving increased attention. The increasing power consumption of complementary-metal-oxide-semiconductor (CMOS) transistors leads to large power dissipation and high chip-temperatures and has implications for device performance and battery life. Scaling of contact area, source/drain junction depth, and contact silicide thickness leads to an increase in the parasitic resistance in the circuit. The fundamental contact-scaling problem arises from the lateral scaling of the contact area in two dimensions. Therefore, the contact resistivity associated with the interface between the source/drain contact and doped contact silicon ultimately becomes the dominant component of the overall source/drain parasitic resistance. There is a need for low barrier height contacts, which can lead to low parasitic resistance and consequently to lower power consumption, heat dissipation and longer battery life times.

Nickel monosilicide has been the material of choice for source/drain contacts to CMOS transistors in recent technology generations. Alloying with nominal amounts of transition metals, such as Pt or Pd, has been employed to overcome the integration challenges faced during processing. These include agglomeration of this low resistivity NiSi phase; and phase transformation to the higher resistivity NiSi₂ phase during fabrication. Local-electrode atom-probe (LEAP) tomography is used in this study to map three-dimensional (3D) distributions of Pt or Pd in Ni monosilicide thin films to obtain insights into the role played by these transition metal elements in phase stabilization. Solid-solutions of Ni_0.95M_0.05 (M = Pd or Pt) thin films on Si (100) substrates are subjected to rapid thermal annealing to form the monosilicide phase. Focused-ion-beam milling is employed to implement the lift-out technique to prepare LEAP tomography samples.

Pt and Pd segregate at the silicide/silicon heterophase interface for Ni_0.95Pt_0.05 and Ni_0.95Pd_0.05 thin films. A measured decrease of the interfacial Gibbs free energy due to segregation at the silicide/silicon interface is most likely responsible for the stabilization of the monosilicide phase at elevated temperatures. Quantitative evidence for short-circuit diffusion of Pt via grain boundaries in the NiSi phase is observed in 3D direct space, providing valuable insights into the kinetics of the reactive diffusion process. The high spatial resolution and the unique 3D nature of the measurements yields accurate and precise measurements of both the lattice and grain boundary diffusivities of Pt. This discovery underscores the importance of interfacial phenomena in the stabilization of this low-resistivity phase and may help explain modification of NiSi texture, grain size, and morphology caused by Pt. The silicide surface work function shifts to the Si valence band edge with Pt incorporation. Additionally, the silicide/Si heterophase interface was reconstructed in three-dimensions on an atomic scale and its chemical roughness evaluated.

This research is supported by the Semiconductor Research Corporation/Global Research Collaboration. The specimens employed were obtained from IBM T. J. Watson Research Center. Acknowledgements are due to IBM Research for an IBM PhD Fellowship for the academic year 2009-2010.