| AVS 57th International Symposium & Exhibition | |
| Graphene Focus Topic | Wednesday Sessions |
| Session GR+MS-WeA |
| Session: | Low Dimensional Carbon Device Manufacturing |
| Presenter: | J.S. Moon, HRL Laboratories, LLC |
| Authors: | J.S. Moon, HRL Laboratories, LLC D. Curtis, HRL Laboratories, LLC M. Hu, HRL Laboratories, LLC S. Bui, HRL Laboratories, LLC D. Wheeler, HRL Laboratories, LLC T. Marshall, HRL Laboratories, LLC D.K. Gaskill, Naval Research Laboratory P.M. Campbell, Naval Research Laboratory P. Asbeck, University of California at San Diego G.G. Jernigan, Naval Research Laboratory J.L. Tedesco, Naval Research Laboratory R.L. Myers-Ward, Naval Research Laboratory C. Eddy Jr., Naval Research Laboratory X. Weng, Penn State University J. Robinson, Penn State University M. Fanton, Penn State University |
| Correspondent: | Click to Email |
In this talk, we present recent progress in epitaxial graphene n-MOSFETs and p-MOSFETs on both SiC and Si substrates for graphene-on-SiC and graphene-on-Si technologies. Both graphene MOSFETs were fabricated in a self-aligned manner on 75 mm wafers and exhibited gate-controlled ambipolar characteristics. For the graphene MOSFETs on SiC substrates, the graphene was grown by Si-sublimation of Si-face 6H-SiC substrates in a commercial Aixtron VP508 epitaxial reactor. For the graphene MOSFETs on Si substrates, the graphene was synthesized by graphitizing a thin 3C-SiC layer grown on float-zone Si (111) substrates using a halogen process. Figure 1 shows sheet resistance maps of 3-inch graphene-on-SiC and graphene-on-Si wafers. Typical Hall mobility ranges from 500 to 2000 cm2/Vs depending on electron carrier density. Both graphene MOSFETs were fabricated with a gate oxide layer and metal gate stack. The gate length was 3 µm. The graphene-on-SiC MOSFETs showed excellent I-V saturation behavior as shown in Figure 2(a). Figure 2(b) shows measured ambipolar behaviors with n-type MOSFET at Vgs = 0 V, while p-type behaviors are observed at Vgs <-1.5 V. An Ion/Ioff ratio of 33 was measured. Figure 2(c) shows measured peak transconductance of 600 mS/mm at Vds = 3 V. Figure 3 shows the extrinsic field-effect mobility of 6000 cm2/Vs for electron and of 3200 cm2/Vs for hole obtained at an effective electric field of ~0.27 MV/cm, approaching Dirac point. The measured graphene field-effect mobility is eight to 10 times higher than that of ITRS Si n-MOSFETs and ~80 times higher than that of ultra-thin-body SOI n-MOSFETs.
The graphene-on-Si MOSFETs are fabricated in a similar manner. Figure 4 shows measured transfer curves of graphene-on-Si MOSFETs, showing ambipolar behaviors with the Dirac point close to zero gate bias, unlike the graphene-on-SiC MOSFETs. The on-state current is measured at 50 to 125 mA/mm with Ion/Ioff ratio of 3 to 2, respectively. This is the highest performance observed among graphene-on-Si technologies so far. RF performance of graphene FETs will be discussed. This work was supported by DARPA, monitored by Dr. M. Fritze, under SPAWAR contract number N66001-08-C-2048.
The views, opinions, and/or findings contained in this article/presentation are those of the author/presenter and should not be interpreted as representing the official views or policies, either expressed or implied, of the Defense Advanced Research Projects Agency or the Department of Defense.
[1] C. Berger et al., Science, vol. 312, p. 1191, 2006; J.S. Moon et al., IEEE EDL., vol 30, p650, 2009