| AVS 57th International Symposium & Exhibition | |
| Graphene Focus Topic | Wednesday Sessions |
| Session GR+MS-WeA |
| Session: | Low Dimensional Carbon Device Manufacturing |
| Presenter: | D.K. Gaskill, U.S. Naval Research Laboratory |
| Authors: | D.K. Gaskill, U.S. Naval Research Laboratory J.S. Moon, HRL Laboratories, LLC G.G. Jernigan, U.S. Naval Research Laboratory J.C. Culbertson, U.S. Naval Research Laboratory J.L. Tedesco, U.S. Naval Research Laboratory J. Robinson, The Pennsylvania State University P.M. Campbell, U.S. Naval Research Laboratory N. Garces, U.S. Naval Research Laboratory V.D. Wheeler, U.S. Naval Research Laboratory J.K. Hite, U.S. Naval Research Laboratory R.L. Myers-Ward, U.S. Naval Research Laboratory C.R. Eddy, Jr., U.S. Naval Research Laboratory A.L. Friedman, U.S. Naval Research Laboratory M. Fanton, The Pennsylvania State University |
| Correspondent: | Click to Email |
The advent of the world’s first epitaxial graphene (EG) RF field effect transistors (FETs), grown on semi-insulating SiC wafers, has generated tremendous interest in the electronics community since devices can be fabricated using conventional photolithographic approaches [1]. Recently, RF FETs have shown an fmax of 14 GHz at 5 Vds for a 2 μm gate width and better results are expected as gate widths are scaled down. To push the performance metrics for wafer-scale EG FETs significantly higher, key materials issues must be addressed. Some of these issues are morphology and thickness control, enhanced mobility, uniformity of sheet carrier density and resistivity, and substrate defects. Here we describe NRL-HRL-Penn State approach in the DARPA CERA program for forming EG via Si sublimation from SiC wafers and the impact of material issues on RF device performance will be discussed.
Epitaxial graphene was synthesized using an Aixtron VP508 reactor on the Si- and C-faces of 4H- and 6H-SiC semi-insulating 0° oriented substrates from 1225 to 1700°C and for 10 to 300 min. Samples were 50.8 and 76.2 mm wafers and 16 x 16 mm2 witnesses. Both in-vacuo (10-6 to 10-4 mbar) and Ar ambient (50-200 mbar) sublimation conditions were investigated. Growth conditions resulted in continuous EG on Si-face witnesses < 1 nm thick as measured by atomic force microscopy, x-ray photoelectron spectroscopy and Raman spectroscopy, whereas growth on C-face witnesses could be varied, depending upon growth conditions, from island formation to continuous sheets > 10 nm thick. Using the witness samples, 300 K mobilities over 2,100 and 27,000 cm2V-1s-1 were found for 10x10 μm2 sized Hall patterns for EG on the Si- and C-face of SiC, respectively.
The growth of EG on 50.8 mm Si-face wafers resulted in excellent relative resistivity uniformity of 2.8% and 300 K Hall mobilities up to 2,700 cm2V-1s-1 were found. Raman spectroscopy mapping of the 2D peak on the wafers determined: (1) the majority of the film was monolayer, (2) two layers of EG could be found at step edges and (3) EG was continuous across the wafer. RF FETs exhibited state-of-the-art ambipolar behavior such as electron field-effect mobility of 6,000 cm2V-1s-1 with Ion/Ioff ratio of 19 and peak transconductance of 600 mS mm-1 per 1 fF μm-2 gate oxide capacitance. The fT●Lg performance metric of 10 GHz●μm was established. Additionally, we will discuss our recent work on EG growth on 76.2 mm wafers as well as the impact of morphological features and Ar ambient controlled graphenization on future RF devices.
Supported by DARPA CERA (N66001-08-C-2048) and ONR.
[1] J.S.Moon et al., IEEE Electron Dev Lett 31, 260 (2010)