Modeling HDP-CVD processes for high quality dielectric film deposition in high aspect ratio device structures remains a challenging task. A number of details such as the reactor geometry, inductive and capacitive power deposition, gas-phase chemistry and surface kinetics need to be addressed in a coupled manner. In this multi-physics approach, a reactor scale model in conjunction with a feature scale model is used to investigate the process dependence of deposition rates across the wafer and within features. Plasma properties, gas flow and deposition at the walls are addressed in the reactor scale model. The resulting film growth inside microscopic trenches is captured in the feature scale model. The reactor geometry is similar to that described in an earlier publication [1]. Data for gas phase and surface reaction kinetics are obtained from published literature [2]. In an earlier work [3], trends in deposition rate at the wafer with inductive power were discussed. In this paper, the impact of reactor scale process parameters such as bias power deposition, gas flow rates and wafer temperature on deposition at the wafer are investigated, and modeling results are compared to experimental data [4].

 

[1] M. Tuszewski and J. A. Tobin, J. Vac. Sci. Technol. A 14, 1096 (1996).

 

[2] E. Meeks, et al, J. Vac. Sci. Technol. A 16, 544 (1998).

 

[3] A. Bhoj, et al, EuroCVD and CVD XVII, 216th Meeting of the Electrochemical Society, Vienna, Austria (2009).

 

 [4] A. Bhoj, P. Kothnur, and R. Kinder, 61st Annual Gaseous Electronics Conference, Dallas, TX (2008).