| AVS 56th International Symposium & Exhibition | |
| Surface Science | Monday Sessions |
| Session SS1+EM-MoA |
| Session: | Semiconductor Surfaces and Interfaces I: Ge and III-V's |
| Presenter: | C.L. Hinkle, University of Texas at Dallas |
| Authors: | C.L. Hinkle, University of Texas at Dallas M. Milojevic, University of Texas at Dallas A.M. Sonnet, University of Texas at Dallas E.M. Vogel, University of Texas at Dallas R.M. Wallace, University of Texas at Dallas |
| Correspondent: | Click to Email |
Field effect transistors (FETs) remain at the heart of integrated circuit technology, and are forecasted to do so for at least the next decade. Silicon has been the material of choice for this purpose, but appears to be reaching significant performance limitations with further device dimension shrinking. As a result, the use of alternative semiconductor materials has again become of interest for FE T s. However, the native oxides (As-O and Ga-O) of these materials have been shown for more than thirty years to be of poor quality for metal-oxide-semiconductor (MOS) device performance. Furthermore, deposition of any gate oxide onto a clean III-V surface results in the oxidation of the substrate to detrimental effects. Despite the extensive research of III-V materials, there is still much to be understood about these oxides. In particular, the individual oxidation states of As (5+ and 3+) and Ga (3+ and 1+) are rarely considered despite evidence that they are quite different in forming defect states.
Recent work [1,2,3] will be presented on the detection and control of each of these surface oxidations states through carefully managed interfacial reactions and depositions on GaAs and InGaAs. The fabrication of MOS capacitors and FETs with these studied interfaces has led to a correlation between the spectroscopy and electrical measurements. An emphasis on controlling or eliminating each oxidation state through a variety of techniques has allowed for a detailed understanding of these native oxides and how each one affects device performance. The presence of the Ga 1+ oxidation state is spectroscopically detected for the first time at these interfaces and a dramatic increase in device performance is demonstrated by controlling the Ga 3+ surface concentration. This work is supported by the FCRP Materials, Structures, and Devices (MSD) Center, SEMATECH, FUSION funded by System IC 2010 (COSAR), The Texas Enterprise Fund, and NIST, Semiconductor Electronics Division.
[1] Hinkle et al., APL 94, 162101 (2009).
[2] Sonnet et al., APL. 93 122109 (2008).
[3] Hinkle et al., IEEE EDL 30, 316 (2009).