| AVS 56th International Symposium & Exhibition | |
| MEMS and NEMS | Friday Sessions |
| Session MN-FrM |
| Session: | Multi-scale Interactions of Materials and Fabrication at the Micro- and Nano-scale |
| Presenter: | A. Kamto, The University of Alabama |
| Authors: | A. Kamto, The University of Alabama R. Divan, Argonne National Laboratory A.V. Sumant, Argonne National Laboratory S.L. Burkett, The University of Alabama |
| Correspondent: | Click to Email |
Vertical interconnects pose an interesting method for heterogeneous integration of electronic technologies allowing three-dimensional (3D) stacking of Microelectromechanical systems and integrated circuit device components [1, 2]. The vertical interconnects, referred to as through-silicon vias (TSVs), begin with formation of blind vias in silicon that are eventually exposed by mechanically lapping and polishing the wafer backside. Inductively coupled plasma (ICP) etching using SF6/O2 gas chemistry at cryogenic temperatures has been investigated as a way to form vias with a tapered sidewall. The point in creating a controlled taper is so that subsequent thin films can be deposited along the sloped sidewall lining the via with insulation, barrier, and seed films. This tapering is necessary if the via lining processes do not provide adequate conformal coverage, a common problem for conventional low temperature deposition processes. In our process for lining vias, plasma enhanced chemical vapor deposited (PECVD) silicon dioxide is used to insulate vias from the surrounding silicon. After insulation, thin films of Ti and Cu are sputter deposited. Ti provides protection from copper migration while the Cu acts as a seed layer for the electrodeposition step. After etching and lining, the vias are filled by reverse pulse plating of Cu. Vias are 20 - 25 μm in diameter and etched using a photoresist mask. The effect of changing gas flow rates, chamber pressure, RF forward power, ICP power, and substrate temperature on etch rate, via profile, and sidewall morphology will be presented. These parameters are critical in optimization of an etch process for vias of specific dimensions to be used in 3D integration.
This work is supported by the College of Engineering at the University of Alabama. Use of the Center for Nanoscale Materials was supported by the U. S. Department of Energy, Office of Science, Office of Basic Energy Sciences, under Contract No. DE-AC02-06CH11357.
References:
[1] N. Ranganathan, D. Y. Lee, L Ebin, N. Balasubramanian, K. Prasad and K.L. Pey, J. Micromech. Microeng. 18, 115028 (2008).
[2] 3D Integration: Technology and Applications, P. Garrou, P. Ramm, and C. Bower, Editors, Vol. 1, 2, Wiley Press (2008).