| AVS 56th International Symposium & Exhibition | |
| Electronic Materials and Processing | Tuesday Sessions |
| Session EM-TuA |
| Session: | High-K Dielectrics on High Mobility Substrates |
| Presenter: | J. Huang, SEMATECH |
| Authors: | N. Goel, Intel Assignee at SEMATECH J. Huang, SEMATECH H. Zhao, University of Texas-Austin I. Ok, SEMATECH J. Lee, University of Texas-Austin P. Majhi, Intel Assignee at SEMATECH P.D. Kirsch, SEMATECH |
| Correspondent: | Click to Email |
With the fundamental limits to the aggressive device scaling in Si CMOS technology, there is significant ongoing research exploring alternate channel materials such as III-V and Ge. These materials hold promise to produce more power efficient transistors compared to current silicon technology. Due to their high carrier mobility, compound III-V semiconductors such as InGaAs and InSb, are being investigated in surface as well as buried channel devices where the inversion or majority carriers determine the device characteristics, respectively. The success of III-V in potential CMOS technology depend on heterogeneous integration on silicon with thinner buffer layers; compatible, low leakage and thermally stable gate dielectric with low interface state density; as well as defect free junctions with low external or access resistance. In addition it is key to develop, standardize and orient various physical and electrical characterization techniques to probe and evaluate the interface and bulk characteristics effectively and correctly at the atomic level. Significant amount of promising research is being done in these modules and there still remain several opportunities to reduce parasitic contributions.