AVS 52nd International Symposium
    Magnetic Interfaces and Nanostructures Thursday Sessions
       Session MI+MS+NS-ThM

Invited Paper MI+MS+NS-ThM9
Processing Technology for Magnetic Random Access Memory

Thursday, November 3, 2005, 11:00 am, Room 204

Session: Advanced Magnetic Storage and Manufacturing Processes
Presenter: M.C. Gaidis, IBM
Authors: M.C. Gaidis, IBM
J.P. Hummel, IBM
S.L. Brown, IBM
S. Kanakasabapathy, IBM
E. O'Sullivan, IBM
S. Assefa, IBM
K. Milkove, IBM
D. Abraham, IBM
Y. Lu, IBM
J.N. Nowak, IBM
P. Trouilloud, IBM
D. Worledge, IBM
W.J. Gallagher, IBM
Correspondent: Click to Email
Magnetic Random Access Memory (MRAM) offers the potential of a universal memory - it can be simultaneously fast, nonvolatile, dense, and high-endurance. Depending on application, these qualities can make MRAM more attractive than SRAM, DRAM, flash, and hard drive memories, with a market measured in the billions of dollars. Small-scale demonstrations have realized much of the potential of MRAM, but scaling the memory to production on economically-profitable 200 or 300 mm wafer sizes creates unique processing challenges heretofore unseen in a large-scale semiconductor fabrication facility. MRAM read operations rely on electron tunneling through a thin (1 nm) insulating barrier between magnetic films. The exponential dependence of tunnel current on barrier thickness imposes requirements for across-wafer film uniformity on the order of 0.01 nm, made possible only by recent developments in deposition technology. To maximize performance, typical magnetic film stack designs can incorporate more than 10 distinct film layers. Very few of these layers can be etched by semiconductor-industry-standard RIE processes, and thus have required development of novel patterning techniques specifically tuned to minimize corrosion and to handle the nonvolatile nature of etch byproducts. The elements in these complex film layers tend to interdiffuse at temperatures below that of back-end-of-line (BEOL) semiconductor processing, thus necessitating the development of low-temperature processes for creating the BEOL wiring and packaging. Although daunting, each of the aforementioned challenges has largely been overcome. This presentation provides an overview of the basic MRAM structure and operation, followed by a discussion of the MRAM-specific processing techniques that have been developed to realize this technology in megabit arrays on 200 mm wafers.