AVS 52nd International Symposium
    Electronic Materials and Processing Thursday Sessions
       Session EM2-ThM

Invited Paper EM2-ThM1
Materials Integration of III-V Heterostructures

Thursday, November 3, 2005, 8:20 am, Room 310

Session: Heteroepitaxy and Low-Dimensional Structures
Presenter: M. Goorsky, University of California, Los Angeles
Authors: M. Goorsky, University of California, Los Angeles
S.L. Hayashi, University of California, Los Angeles
A. Noori, University of California, Los Angeles
R.S. Sandhu, University of California, Los Angeles and Northrop Grumman Space Technology
A. Cavus, Northrop Grumman Space Technology
C. Monier, Northrop Grumman Space Technology
M. Lange, Northrop Grumman Space Technology
M. Wojtowicz, Northrop Grumman Space Technology
T. Block, Northrop Grumman Space Technology
A. Gutierrez-Aitken, Northrop Grumman Space Technology
Correspondent: Click to Email
III-V wafer bonded structures satisfy requirements for electronic device structures that simultaneously possess a large surface lattice parameter (e.g., near that of InAs) and a high substrate resistivity. The objectives of the research are to address the fabrication of III-V composite wafer bonding with the ultimate goal of producing virtual substrates for advanced III-V devices. Graded buffer layers are one key technological step. Very thin InAlAs graded buffer layer structures were produced for virtual InAlAs substrate applications. The rapid kinetics of strain relaxation in In@sub x@Al@sub 1-x@As graded buffer layers (GBLs) was exploited to produce thin (0.21 µm - 0.90 µm) buffer layers graded from the InP substrate to 6.0 Å. GBL layers as thin as 0.21 µm showed full strain relaxation and GBL layers as thin as 0.45 µm showed similar growth mode, surface roughness, and strain relaxation as thicker GBL structures. The threading dislocation density was low (mid-10@super 6@ cm@super -2@) for the 0.45 µm and the 0.90 µm buffer layers but there was evidence of non-uniform threading dislocation distribution for the 0.21 µm buffer structures. The feasibility of aggressive grading for other III-V systems will also be addressed. For some applications, even a thin GBL - upon which device structures are grown - is not feasible for device applications. To address the issue of limited GBL thickness, hydrogen exfoliation ("Smart-Cut") has been assessed to transfer thin films of InP, InAs, or 6.0Å lattice parameter layers to high resistivity substrates. We have developed a strategy for implantation and exfoliation based on the nucleation and growth of mechanical cracks at the projected range of the implant. This method has led to reproducible exfoliation and successful transfer of a wide variety of semiconductor materials. Damage-free chemical-mechanical polishing (CMP) has also been developed to produce low roughness (< 1 nm r.m.s) surfaces for subsequent epitaxial deposition. Another issue associated with composite wafers is the coefficient of thermal expansion (CTE) differences between the bulk substrate and the transferred layer. We have incorporated the temperature-dependent CTE values into force-balance equations to determine the thermodynamic stability of heterostructures based on these materials. The stability criteria have been experimentally confirmed. Examples of device structures on graded buffer layers and transferred layers will be shown to demonstrate the feasibility of this approach for the integration of III-V heterostructures.