AVS 51st International Symposium
    Nanometer-scale Science and Technology Thursday Sessions
       Session NS1-ThM

Paper NS1-ThM5
Scanning Tunneling Microscopy Electronic Characterization of a Nano Device for Quantum Computing

Thursday, November 18, 2004, 9:40 am, Room 213C

Session: Nanoscale Fabrication
Presenter: M.E. Hawley, Los Alamos National Laboratory
Authors: M.E. Hawley, Los Alamos National Laboratory
G.W. Brown, Los Alamos National Laboratory
H. Grube, Los Alamos National Laboratory
Correspondent: Click to Email
Quantum computation is a revolutionary new paradigm that has seen tremendous growth since 1994. The quest to build a quantum computer (QC) has been inspired by its recognized formidable computational potential. The long-term goal in this quest is a large scale, fast, parallel and easily fabricated QC. Although a number of ingenious schemes have been proposed, silicon-based solid-state proposals, using nuclear or electron spins of dopants such a phosphorus as qubits, are attractive because of the long spin relaxation times and their scaleability and integratability with existing silicon technology. We have been working on such a device based on a proposal by B. Kane (Nature 393, 133 (1998), in which buried P atoms placed 20 nm apart act as quantum bits entangled through exchange interactions, atomically placed using Scanning tunneling microscope (STM) lithographic techniques on a hydrogen resist layer. This effort requires dosing the Si(100) surface with phosphine molecules and annealing the phosphorus into the silicon surface. STM-based atomic level lithography methods provides us with the added capability of characterizing the local electronic environment of the dopants. In this talk, Iâ?Tll describe our particular effort to fabricate a QC and the charge imaging technique we are using to image buried phosphorus dopants and charged defects that could potentially interfere with the operation of such a QC device as well as any other nano scale device on the silicon surface.}