AVS 51st International Symposium
    Nanometer-scale Science and Technology Thursday Sessions
       Session NS1-ThM

Paper NS1-ThM4
Fabrication and Electrical Characterization of 2D Dopant Nanoelectronic Devices in Si

Thursday, November 18, 2004, 9:20 am, Room 213C

Session: Nanoscale Fabrication
Presenter: J.S. Kline, University of Illinois at Urbana-Champaign
Authors: J.S. Kline, University of Illinois at Urbana-Champaign
S.J. Robinson, University of Illinois at Urbana-Champaign
J.R. Tucker, University of Illinois at Urbana-Champaign
J.-Y. Ji, Utah State University
T.-C. Shen, Utah State University
C. Yang, University of Utah
R.-R. Du, University of Utah
Correspondent: Click to Email
The integration of nanoscale devices with Si-based microelectronics presents a major challenge in nanotechnology. We address this issue by employing STM patterned P donors as the building block for all-epitaxial nanoscale devices on pre-fabricated templates. To preserve the As-implanted contacts, we have developed a low-temperature UHV process using 300eV Ar ion sputtering and sub-700°C annealing to prepare atomically flat and clean surfaces for STM lithography. Differences in surface features and tunneling spectroscopy allow the registration of the STM to the template. After STM nanolithography, P donors are selectively deposited onto the patterned area by phosphine exposure. Subsequent Si low-temperature deposition and 500°C annealing forms an epitaxial overlayer and activates the dopant atoms. Electron transport measurements at 4.2K for several 2-terminal devices including two-dimensional P wires 10-50nm wide and 30-700nm long indicate resistivity of the wires is in the order of 20k@ohm@/sq. Quantum coherence length and the implication of the oscillations in the magnetoresistance at 0.3K will be discussed. In addition, the fabrication and measurement of tunnel junctions is currently in progress and will also be reported. This work is supported by DARPA-QuIST program under ARO contract DAAD 19-01-1-0324.