AVS 51st International Symposium
    Nanometer-scale Science and Technology Tuesday Sessions
       Session NS-TuP

Paper NS-TuP30
Fabrication of MOS Structure with NiSi@sub 2@ Nanocrystals Embedded in Silicon Dioxide

Tuesday, November 16, 2004, 4:00 pm, Room Exhibit Hall B

Session: Poster Session
Presenter: P.-H. Yeh, National Tsing Hua University, Taiwan
Authors: P.-H. Yeh, National Tsing Hua University, Taiwan
C.H. Yu, National Tsing Hua University, Taiwan
L.J. Chen, National Tsing Hua University, Taiwan
H.H. Wu, National Sun Yat-Sen University, Taiwan
T.-C. Chang, National Sun Yat-Sen University, Taiwan
P.T. Liu, National Nano Device Laboratory, Taiwan
Correspondent: Click to Email
A metal-oxide-semiconductor (MOS) structure with NiSi@sub 2@ nanocrystals embedded in the SiO@sub 2@ layer has been fabricated. From the TEM micrograph and diffraction pattern, the nanocrystals were identified to be NiSi@sub 2@. The mean size and the aerial density of the NiSi@sub 2@ nanocrstals were estimated to be ~ 7.6 nm and 3.3 x 10@super 11@/cm@super 2@, respectively. A pronounced capacitance-voltage hysteresis is observed with a memory window of 1 V under the 2-V programming voltage. The process of the structure is compatible with the current manufacturing technology of semiconductor industry. The structure represents a viable candidate for low-power sub-100 nm nonvolatile memory devices.