Integrated circuit performance improvements have been achieved largely by aggressive shrinking of the silicon transistor and metal interconnect dimensions. Future technology generations will require even greater innovation to continue the performance trend. New materials, device structures, and integration schemes will all play roles in advancing CMOS technology. Novel nanometer-scale patterning techniques will be critical to this success. This talk will give an overview of nanometer-scale patterning needs of the semiconductor industry and highlight several novel solutions. Direct write scanning probe lithography (SPL) is a high-resolution patterning technique that uses a sharp tip in close proximity to a sample to pattern nanometer-scale features. Low energy electrons field emitted from a probe tip can be used to expose polymer resists with sub-30-nm resolution and nanometer-scale alignment registration. In comparison to electron beam lithography, SPL has wider exposure latitude, improved linearity, and reduced proximity effects. Material self assembly provides an alternative means for pattern formation at the nanometer-scale. With feature sizes defined by fundamental molecular properties, self assembly can access dimensions and densities beyond the capabilities of conventional patterning techniques. Our work has focused on identifying and demonstrating key applications of self assembly. In one example, we enhanced the capacity of thin film metal-oxide-semiconductor devices using nanostructured electrodes patterned by self assembly. We have also demonstrated the use of material self assembly in facilitating continued scaling of non-volatile FLASH memories. These high resolution patterning processes offer innovative solutions to existing challenges in microelectronics and are well suited to enabling enhanced device performance and functionality by augmenting the available tool kit for manufacturing.