IUVSTA 15th International Vacuum Congress (IVC-15), AVS 48th International Symposium (AVS-48), 11th International Conference on Solid Surfaces (ICSS-11)
    Photonics Materials Topical Conference Thursday Sessions
       Session PH-ThA

Paper PH-ThA3
Silica Deep Etching with Vertical and Smooth Sidewall and Reduced RIE Lag

Thursday, November 1, 2001, 2:40 pm, Room 120

Session: Photonic Materials: Applications and Processing
Presenter: D.Y. Choi, Samsung Electronics, Korea
Authors: D.Y. Choi, Samsung Electronics, Korea
J.H. Lee, Samsung Electronics, Korea
D.S. Kim, Samsung Electronics, Korea
S.T. Jung, Samsung Electronics, Korea
Correspondent: Click to Email
Silica waveguides are very important for use in Planar Lightwave Circuits(PLC) because of its low loss and inherent compatibility with silica optical fibers. Deep silica etching(>30um) is necessary when silica PLC is used as a platform to integrate with active devices(LD, PD, SOA, etc.). To lower propagation loss, polarization dependent loss(PDL), and reflectance at waveguide end facet(junction between waveguide and active device), vertical and smooth sidewalls are required. In this work the profile and sidewall roughness of etched waveguides were investigated. Vertical profile was obtained when etching mask was thickened and polymer deposition on sidewall was promoted. But sidewall roughness was increased as deposited polymer thickened. When the clamp in the plasma chamber was changed from alumina to silicon, vertical and smooth sidewall was obtained. RIE lag(Aspect ratio Dependent Etching) becomes important in deep silica etching. We investigated the extent of RIE lag as a function of aspect ratio of trench structures, etching depth, bias power, and pressure. RIE lag increased irrespective of etching depth as aspect ratio increased. When process pressure was high and Si clamp was used, nearly RIE lag-free trench was etched.