This continued scaling of lateral dimensions of Si field effect transistors to increase device packing densities, and to improve high frequency performance requires proportional decreases in the effective thickness of the gate dielectric. When this equivalent oxide thickness, EOT, is reduced to < 2.5 to 3 nm, direct tunneling emerges as an important factor in device performance and reliability. Direct tunneling at bias voltages for channel inversion exceeds 1A-cm-2 at EOT ~1.5 to1.6 nm, and defines a limitation for thermally-grown SiO@sub 2@ for high power devices. Limitations for portable devices are much more restrictive. The obvious solution for extending EOT to significantly smaller values ~0.5-0.6 nm is to introduce deposited thin film alternative gate dielectrics with higher dielectric constants. This is a formidable task, since the performance and reliability of devices with thermally-grown SiO@sub 2@ derives from i) the low density of defects, trapping sites and fixed charge, at the Si-SiO@sub 2@ interface, and the ii) the low density of electrically-active defects in the SiO@sub 2@ film. Deposited gate dielectrics will then require separate and independent control of the properties of Si-dielectric interface, and the thin film alternative dielectric generally in stacked configurations. Introduction of alternative gate dielectrics will proceed in two steps, i) replacement of SiO@sub 2@ with deposited silicon oxynitride alloys and silicon nitride, extending EOT to ~ 1.1 nm, and then iii) replacement of the dielectrics of i) with metal-oxide and silicate thin films with dielectrics constants in excess of 10. This paper will address issues relevant to single layer and composite structures for both groups of replacement dielectrics identified above.