AVS 46th International Symposium
    Nanometer-scale Science and Technology Division Monday Sessions
       Session NS-MoM

Paper NS-MoM7
Experimental and Theoretical Coincidence in Room Temperature Single Electron Transistor Formed by AFM Nano-Oxidation Process

Monday, October 25, 1999, 10:20 am, Room 6C

Session: Nanotechnology
Presenter: Y. Gotoh, Electrotechnical Laboratory MITI, Japan
Authors: Y. Gotoh, Electrotechnical Laboratory MITI, Japan
K. Matsumoto, Electrotechnical Laboratory MITI, Japan
T. Maeda, Electrotechnical Laboratory MITI, Japan
S. Manalis, Massachusetts Institute of Technology
J. Harris, Stanford University
C. Quate, Stanford University
Correspondent: Click to Email
The experimental results of the room temperature operated single electron transistor (SET) were simulated using orthodox theory and 3 dimensional Poisson's equation. The simulated results coincided well with the experimental results. The planer type SET has been fabricated by oxidizing the surface of 2nm-thick titanium (Ti) metal that was on the atomically flat @ALFA@-Al@sub 2@O@sub 3@ substrate using the pulse mode AFM nano-oxidation process@super 1)@. The narrow oxidized Ti wire works as a tunnel junction for SET. The fabricated SET shows Coulmb oscillation characteristic even at room temperature at the drain bias of V@sub D@=0.3V when the gate bias was changed from V@sub G@=0 to 10V, and 5 oscillation peaks were observed with the periods of ~2V. The drain current was modulated by the gate bias and oscillates from 2.4pA to 3pA. Therefore, the modulation rate is ~20%. Using the orthodox theory, the experimental Coulmb oscillation was fitted using the parameters of the gate capacitance CG=8x10@super-20@F and the tunnel junction capacitances C@sub 1@=C@sub 2@=2.9x10@super -19@F. The simulated result represents well the experimental one, i.e. the position and the number of the Coulmb oscillation peaks and the modulation rate of the drain current coincide with the experiment of ones. Furthermore, tunnel junction capacitances were calculated by solving the 3D Poisson's equation for the structures of fabricated SET. In the calculation, the error tolerance of 0.01% was used. The calculated tunnel junction capacitances is found to be C@sub 1@=C@sub 2@=4x10@super-19@F which is almost coincide with the parameter used in the orthodox simulation. For further improvement of SET characteristics, an ultra sharp multi-wall carbon nanotube AFM tip was introduced for the AFM nano-oxidation process to reduce the oxide wire width down to 10~15nm to increase a tunnel current to improve S/N ratio of SET. 1) K. Matsumoto, Proceedings of IEEE Vol. 85, No. 4, p. 612 (1997).