AVS 46th International Symposium
    Magnetic Interfaces and Nanostructures Technical Group Wednesday Sessions
       Session MI+EM-WeM

Invited Paper MI+EM-WeM3
High Performance Demonstration of Magnetic Tunnel Junction Random Access Memory*

Wednesday, October 27, 1999, 9:00 am, Room 618/619

Session: Spin-Dependent Tunneling and Transport
Presenter: W.J. Gallagher, IBM
Authors: W.J. Gallagher, IBM
S.L. Brown, IBM
Y. Lu, IBM
E.J. O'Sullivan, IBM
P.L. Trouilloud, IBM
D.A. Abraham, IBM
J. Bucchignano, IBM
R.H. Koch, IBM
Y.H. Lee, IBM
R. Robbertazzi, IBM
M. Rooks, IBM
J. Yoon, IBM
R.A. Wanner, IBM
S.S.P. Parkin, IBM
D. Pearson, IBM
K.P. Roche, IBM
M.G. Samant, IBM
P.M. Rice, IBM
A. Lee, IBM
R.E. Scheuerlein, IBM
Correspondent: Click to Email
We describe a magnetic tunnel junction (MTJ) RAM demonstration involving the integration of 0.25 µm CMOS technology with a special research-scale magnetic tunnel junction "back end." The magnetic back end is based upon state of the art mutilayer magnetic growth technology available on a research scale. For the demonstration, the wafers were cut into one-inch squares for depositions of bottom-pinned exchange biased magnetic tunnel junctions. The samples were then processed through four additional lithographic levels to complete the circuits. Special care was required to achieve fine lithography on the one-inch pieces aligned to the underlying circuits. Both deep uv stepper lithography and e-beam lithography were utilized. Patterning of the magnetic layers involved physical removal of the magnetic material by means of ion beam milling, an etching process not commonly used in semiconductor technology. Redeposition, which accompanies ion milling and is exacerbated in dense arrays, had to be carefully controlled with combinations of angled mills in order to minimize the occurrence of junction shorts and maximize the yield of working bits. Key performance aspects demonstrated in 1 K bit arrays included reads and writes in less than 10 ns and nonvolatility. These results suggest that MTJ MRAM might simultaneously provide much of the functionality now provided separately by SRAM, DRAM, and NVRAM. . @FootnoteText@ @footnote *@ Work supported in part by DARPA contract MDA972-96-C-0014.